METHOD AND APPARATUS FOR ADJUSTING DEMARCATION VOLTAGES BASED ON CYCLE COUNT METRICS

• US 20190103160A1
• Filed: 09/29/2017
• Published: 04/04/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Fang, Wei, Damle, Prashant S., Gajera, Nevil N.
• Granted Patent: US 10,777,271 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/005 Read using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

In one embodiment, an apparatus comprises a first memory array comprising a plurality of phase change memory (PCM) cells; and a controller to track a first cycle count metric based at least in part on a number of writes performed to at least a portion of the first memory array; and adjust, based on the first cycle count metric, a demarcation voltage to be applied during read operations performed on PCM cells of the first memory array.

Claims

1. An apparatus comprising:

a first memory array comprising a plurality of phase change memory (PCM) cells; and

a controller to;

track a first cycle count metric based at least in part on a number of writes performed to at least a portion of the first memory array; and

adjust, based on the first cycle count metric, a first demarcation voltage comprising an initial demarcation voltage to be applied during read operations performed on PCM cells of the first memory array, wherein the first demarcation voltage is adjusted downward in response to a determination that the first cycle count metric has crossed a first threshold; and

adjust the first demarcation voltage further downward in response to a determination that the first cycle count metric has crossed a second threshold, the second threshold having a value greater than a value of the first threshold.

2. The apparatus of claim 1, the controller to:

track a second cycle count metric based at least in part on a number of writes performed to at least a portion of a second memory array comprising a second plurality of PCM cells, wherein a first memory chip comprises the first memory array and a second memory chip comprises the second memory array; and

adjust, based on the second cycle count metric, a demarcation voltage to be applied during read operations performed on PCM cells of the second memory array.

3. The apparatus of claim 1, wherein the first demarcation voltage is to be applied during read operations performed on PCM cells of a plurality of memory arrays of a semiconductor chip.

4. The apparatus of claim 1, wherein the controller is to adjust, based on the first cycle count metric, a plurality of demarcation voltages to be applied during a read operation performed on PCM cells of the first memory array.

5. The apparatus of claim 1, wherein the first demarcation voltage is adjusted in response to a determination that the first cycle count metric has crossed a threshold.

6. The apparatus of claim 1, wherein the first cycle count metric is a μ

−

3σ

write cycle count of a distribution of write cycle counts of a plurality of groups of PCM cells.

7. The apparatus of claim 1, wherein the first cycle count metric is an average of write cycle counts of a plurality of groups of PCM cells.

8. The apparatus of claim 1, wherein the first cycle count metric is a maximum write cycle count of a plurality of groups of PCM cells.

9. The apparatus of claim 1, wherein the controller is to:

track a second cycle count metric based at least in part on the number of writes performed to at least a portion of the first memory array, wherein the second cycle count metric is a different type of metric than the first cycle count metric; and

adjust, based on a determination that the second cycle count metric has crossed a third threshold, the first demarcation voltage downward.

10. The apparatus of claim 1, wherein the controller is to derive the at least one cycle count metric from information tracked by the controller to perform wear leveling among multiple memory arrays.

11. The apparatus of claim 1, wherein the first cycle count metric is based on a write cycle count for a slice of PCM cells of the first memory array, wherein the write cycle count is to be stored in the slice.

12. The apparatus of claim 1, further comprising a battery communicatively coupled to a processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.

13. A method comprising:

tracking a first cycle count metric based at least in part on a number of writes performed to at least a portion of a first memory array comprising a plurality of memory cells; and

adjusting, based on the first cycle count metric, a first demarcation voltage comprising an initial demarcation voltage to be applied during read operations performed on memory cells of the first memory array, wherein the first demarcation voltage is adjusted downward in response to a determination that the first cycle count metric has crossed a first threshold; and

adjusting the first demarcation voltage further downward in response to a determination that the first cycle count metric has crossed a second threshold, the second threshold having a value greater than a value of the first threshold.

14. The method of claim 13, further comprising:

tracking a second cycle count metric based at least in part on a number of writes performed to at least a portion of a second memory array comprising memory cells, wherein a first memory chip comprises the first memory array and a second memory chip comprises the second memory array; and

adjusting, based on the second cycle count metric, a demarcation voltage to be applied during read operations performed on memory cells of the second memory array.

15. The method of claim 13, further comprising applying the first demarcation voltage during read operations performed on memory cells of a plurality of memory arrays of a semiconductor chip.

16. The method of claim 13, further comprising adjusting, based on the first cycle count metric, a plurality of demarcation voltages to be applied during a read operation performed on memory cells of the first memory array.

17. A non-transitory machine readable storage medium having instructions stored thereon, the instructions when executed by a machine to cause the machine to:

track a first cycle count metric based at least in part on a number of writes performed to at least a portion of a first memory array comprising memory cells; and

adjust, based on the first cycle count metric, a first demarcation voltage comprising an initial demarcation voltage to be applied during read operations performed on memory cells of the first memory array, wherein the first demarcation voltage is adjusted downward in response to a determination that the first cycle count metric has crossed a first threshold; and

adjust the first demarcation voltage further downward in response to a determination that the first cycle count metric has crossed a second threshold, the second threshold having a value greater than a value of the first threshold.

18. The medium of claim 17, the instructions when executed to cause the machine to:

track a second cycle count metric based at least in part on a number of writes performed to at least a portion of a second memory array comprising memory cells, wherein a first memory chip comprises the first memory array and a second memory chip comprises the second memory array; and

adjust, based on the second cycle count metric, a demarcation voltage to be applied during read operations performed on memory cells of the second memory array.

19. The medium of claim 17, wherein the adjusted first demarcation voltage is to be applied during read operations performed on memory cells of a plurality of memory arrays of a semiconductor chip.

20. The medium of claim 17, the instructions when executed to cause the machine to adjust, based on the first cycle count metric, a plurality of demarcation voltages to be applied during a read operation performed on memory cells of the first memory array.

21. A system comprising:

a controller comprising circuitry to;

track a first cycle count metric based at least in part on a number of writes performed to at least a portion of a memory array comprising a plurality of memory cells;

adjust, based on the first cycle count metric, a first demarcation voltage comprising an initial demarcation voltage to be applied during read operations performed on memory cells of the memory array, wherein the first demarcation voltage is adjusted downward in response to a determination that the first cycle count metric has crossed a first threshold; and

adjust the first demarcation voltage further downward in response to a determination that the first cycle count metric has crossed a second threshold, the second threshold having a value greater than a value of the first threshold.

22. The system of claim 21, further comprising the memory array.

23. The system of claim 21, further comprising a central processing unit of a host device, the central processing unit to send a read command to the controller.

24. The system of claim 23, further comprising a battery communicatively coupled to the central processing unit, a display communicatively coupled to the central processing unit, or a network interface communicatively coupled to the central processing unit.