Semiconductor devices, and a Method for Forming a Semiconductor device

• US 20190103333A1
• Filed: 09/29/2017
• Published: 04/04/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel IP Corporation (Intel Corporation)
• Inventors: Mahnkopf, Reinhard, Wolter, Andreas, Koller, Sonja
• Granted Patent: US 10,535,578 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/3738 Semiconductor materials
• CPC Class Codes: H01L 23/4985 Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A semiconductor device includes a plurality of circuit regions formed at a circuit semiconductor layer of a semiconductor die. The semiconductor device includes an etch stop layer of the semiconductor die arranged between the circuit semiconductor layer of the semiconductor die and a handling layer of the semiconductor die. The semiconductor device includes one or more trench structures extending through the handling layer of the semiconductor die. The one or more trench structures extends to at least the etch stop layer and to at most the circuit semiconductor layer of the semiconductor die.

Claims

1. A semiconductor device, comprising:

a plurality of circuit regions formed at a circuit semiconductor layer of a semiconductor die;

an etch stop layer of the semiconductor die arranged between the circuit semiconductor layer of the semiconductor die and a handling layer of the semiconductor die; and

one or more trench structures extending through the handling layer of the semiconductor die, wherein the one or more trench structures extends to at least the etch stop layer and to at most the circuit semiconductor layer of the semiconductor die.

2. The semiconductor device according to claim 1, wherein a minimal lateral dimension of the one or more trench structures is larger than 1 μ

m.

3. The semiconductor device according to claim 1, wherein a minimal depth of the one or more trench structures is larger than 50% of an average thickness of the semiconductor die.

4. The semiconductor device according to claim 1, wherein a minimal depth of the one or more trench structures is larger than 10 μ

m.

5. The semiconductor device according to claim 1, wherein a maximal thickness of the circuit semiconductor layer of the semiconductor die is less than 10 μ

m.

6. The semiconductor device according to claim 1, wherein the plurality of circuits regions of the circuit semiconductor layer are located between intervening regions of a plurality of intervening regions of the circuit semiconductor layer,

wherein the circuit regions of the plurality of circuit regions have a high transistor density, and

wherein the intervening regions of the plurality of intervening regions have a low transistor density.

7. The semiconductor device according to claim 1, wherein the plurality of circuits regions of the circuit semiconductor layer are located between intervening regions of a plurality of intervening regions of the circuit semiconductor layer,

wherein the circuit regions of the plurality of circuit regions carries a high current density during an on-state of the semiconductor device, and

wherein the intervening regions of the plurality of intervening regions carries a low current density during the on-state of the semiconductor device.

8. The semiconductor device according to claim 1, wherein the one or more trench structures comprise a plurality of trenches in a cross section of the semiconductor die, wherein the trenches of the plurality of trenches are located between portions of the handling layer.

9. The semiconductor device according to claim 8, wherein the plurality of trenches are arranged at locations in the handling layer corresponding to locations of the plurality of circuit regions at the circuit semiconductor layer of the semiconductor die.

10. The semiconductor device according to claim 8, wherein the plurality of trenches are arranged at locations in the handling layer so that a bottom of each trench of the plurality of trenches laterally overlaps a lateral area of a circuit region of the plurality of circuit regions.

11. The semiconductor device according to claim 1, wherein thermally conductive filler material is arranged in the one or more trench structures, wherein a thermal conductivity of the thermally conductive filler material is at least 2 times larger than a thermal conductivity of the handling layer of the semiconductor die.

12. The semiconductor device according to claim 11, wherein the thermally conductive filler material comprises a metal or a liquid.

13. The semiconductor device according to claim 8, wherein the plurality of trenches of the one or more trench structures are arranged at locations in the handling layer corresponding to locations of the plurality of intervening regions at the circuit semiconductor layer of the semiconductor die.

14. The semiconductor device according to claim 13, further comprising a flexible cover structure covering at least the back surface of the semiconductor die, wherein the one or more trench structures is filled with air, nitrogen or a noble gas.

15. The semiconductor device according to claim 13, further comprising a flexible cover structure covering at least the back surface of the semiconductor die, wherein an elastic filler material is arranged in the one or more trench structures.

16. The semiconductor device according to claim 14, further comprising a curved or flexible carrier substrate, wherein the semiconductor die is connected to a surface of the curved or flexible carrier substrate via a front surface of the semiconductor die.

17. The semiconductor device according to claim 13, wherein the plurality of trenches of the one or more trench structures are arranged so that the semiconductor die is a bendable semiconductor die.

18. The semiconductor device according to claim 13, wherein the semiconductor device is at least one device selected from the following group of devices:

a wearable device and a display device.

19. The semiconductor device according to claim 1, wherein the semiconductor die is a silicon-on-insulator (SOI) die.

20. A semiconductor device, comprising:

a plurality of circuit regions formed at a circuit semiconductor layer of a semiconductor die;

an etch stop layer of the semiconductor die arranged between the circuit semiconductor layer of the semiconductor die and a handling layer of the semiconductor die; and

one or more trench structures extending into the handling layer from a back side of the semiconductor die, wherein the one or more trench structures are filled with gas or elastic material; and

a cover structure arranged at the back side of the semiconductor die and covering the one or more trench structures.

21. The semiconductor device according to claim 20, wherein the one or more trench structures extends to at least the etch stop layer and to at most the circuit semiconductor layer of the semiconductor die.

22. The semiconductor device according to claim 20, wherein the one or more trench structures are arranged so that the semiconductor die is a bendable semiconductor die.

23. A method for forming a semiconductor die, the method comprising:

forming a plurality of circuit regions at a circuit semiconductor layer of a semiconductor die;

forming one or more trench structures extending through a handling layer of the semiconductor die, wherein the one or more trench structures extends to at least an etch stop layer of the semiconductor die and to at most a circuit semiconductor layer of the semiconductor die,

wherein the etch stop layer of the semiconductor die is arranged between the circuit semiconductor layer of the semiconductor die and a handling layer of the semiconductor die.

24. The method according to claim 23, wherein the plurality of circuits regions of the circuit semiconductor layer are formed between intervening regions of a plurality of intervening regions of the circuit semiconductor layer,

wherein the circuit regions of the plurality of circuit regions have a high transistor density, and

wherein the intervening regions of the plurality of intervening regions have a low transistor density.

25. The method according to claim 23, wherein the one or more trench structures formed comprise a plurality of trenches in a cross section of the semiconductor die, wherein the trenches of the plurality of trenches are located between portions of the handling layer.