PACKAGE ON PACKAGE WITH INTEGRATED PASSIVE ELECTRONICS METHOD AND APPARATUS

• US 20190103388A1
• Filed: 09/29/2017
• Published: 04/04/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kim, Hyoung Il
• Granted Patent: US 10,446,533 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/1815 Shape

Abstract

The present application relates to devices and techniques for a package on package multi-package integrated circuit. A component of the integrated circuit maybe located in a void formed in a circuit package of the multi-package integrated circuit. The void may be formed by fabricating a void structure with an internal void corresponding to the component. The void structure may be bonded to a first substrate of a first package in the multi-package integrated circuit. The first substrate and void structure may be encased in a mold compound. A sacrificial layer may be removed, exposing the void in the void structure. The component may be, for example, a through mold via. The first package may be coupled to a second package. Multi-package integrated circuit assemblies fabricated pursuant to the disclosure herein may comprise a higher density of electronic components, including passive electronic components.

Claims

1. A method of fabricating a multi-package integrated circuit comprising:

preparing a void structure comprising a void, wherein the void is sized to accommodate a passive electrical component;

preparing a bottom circuit package comprising a bottom circuit package substrate and comprising a first integrated circuit and the void structure in a die side layer of the bottom circuit package;

removing a sacrificial layer from the die side layer of the bottom circuit package to expose the void in the void structure;

preparing a top circuit package comprising a top circuit package substrate and a second integrated circuit in a die side layer of the top circuit package substrate;

positioning or forming the passive electrical component in the void;

electrically coupling the passive electrical component to an interface side of the top circuit package substrate; and

mounting the top circuit package substrate to the bottom circuit package substrate with the passive electrical component in the void.

2. The method according to claim 1, further comprising electrically coupling the passive electrical component to the interface side of the top circuit package substrate before mounting the top circuit package substrate to the bottom circuit package with the passive electrical component in the void.

3. The method according to claim 1, wherein the passive electrical component comprises at least one of a resistor, capacitor, power component, or through mold via (TMV).

4. The method according to claim 3, further comprising forming the TMV in the void and wherein at least one of electrically coupling the TMV to the interface side of the top circuit package substrate or mounting the top circuit package substrate to the bottom circuit package with the passive electrical component in the void is performed by reflow soldering.

5. The method according to claim 4, wherein forming the TMV in the void comprises filling the void with a conductor, capping the conductor with a solder paste, and wherein reflow soldering melts the solder paste.

6. The method according to claim 1, further comprising preparing the void structure with a vertical wall of the void in the void structure perpendicular to a horizontal floor of the void in the void structure.

7. The method according to claim 1, wherein preparing the void structure comprises preparing the void structure from a material of the bottom circuit package.

8. The method according to claim 1, wherein removing a sacrificial layer from the die side layer of the bottom circuit package to expose the void in the void structure comprises removing the sacrificial layer by grinding.

9. The method according to claim 1, wherein the void is a first void, the passive electrical component is a first passive electrical component and further comprising forming a second void in the bottom circuit package by a void forming process and inserting or forming a second passive electrical component in the second void.

10. The method according to claim 9, wherein the void forming process comprises at least one of mechanical drilling, laser drilling, or chemical etching.

11. The method according to claim 1, wherein the mounting the top circuit package substrate to the bottom circuit package substrate is with a first ball grid array and wherein mounting the top circuit package substrate to the bottom circuit package with the passive electrical component in the void with the first ball grid array comprises electrically coupling the top circuit package and the bottom circuit package with the first ball grid array, wherein the bottom circuit package comprises an interface side of a bottom circuit package substrate, and electrically coupling the interface side of the bottom circuit package substrate to a motherboard with a second ball grid array.

12. The method according to claim 11, wherein the second ball grid array forms more electrical contacts between the interface side of the bottom circuit package substrate and the motherboard than the first ball grid array forms between the interface side of the top circuit package substrate and the bottom circuit package.

13. A multi-package integrated circuit comprising a top circuit package and a bottom circuit package, wherein the top circuit package comprises a first integrated circuit, a top circuit package substrate, and a passive electrical component electrically coupled to an interface side of the top circuit package substrate, wherein the bottom circuit package comprises a second integrated circuit and a void, and wherein the top circuit package and the bottom circuit package are electrically coupled and wherein the passive electrical component is positioned in or formed in the void.

14. The multi-package integrated circuit of claim 13, wherein the void is a hollow nucleus of a void structure molded into the bottom circuit package and wherein the void structure is made from a material of the bottom circuit package.

15. The multi-package integrated circuit of claim 13, wherein the void is a first void, the passive electrical component is a first passive electrical component and further comprising a second void in the bottom circuit package and a second passive electrical component in the second void.

16. The multi-package integrated circuit of claim 13, wherein the passive electrical component comprises at least one of a resistor, capacitor, power component, or through mold via (TMV).

17. The multi-package integrated circuit of claim 16, wherein the passive electrical component is electrically coupled to the bottom circuit package.

18. The multi-package integrated circuit of claim 16, wherein the bottom circuit package comprises a bottom circuit package substrate and wherein the TMV comprises vertical walls perpendicular to the top circuit package substrate and the bottom circuit package substrate.

19. The multi-package integrated circuit of claim 13, wherein the top circuit package and the bottom circuit package are electrically coupled by a first ball grid array and wherein an interface side of a bottom circuit package substrate of the bottom circuit package is mounted to a motherboard by a second ball grid array.

20. A computer device comprising:

a top circuit package, a bottom circuit package, and a motherboard, wherein the top circuit package comprises a first integrated circuit, a top circuit package substrate, and a passive electrical component electrically coupled to an interface side of the top circuit package substrate, wherein the bottom circuit package comprises a second integrated circuit and a void, wherein the top circuit package and the bottom circuit package are electrically coupled by a first ball grid array, wherein the passive electrical component is positioned in or formed in the void, and wherein an interface side of a bottom circuit package substrate of the bottom circuit package is mounted to the motherboard by a second ball grid array.

21. The computer device of claim 20, wherein the void is a hollow nucleus of a void structure molded into the bottom circuit package and wherein the void structure is made from a material of the bottom circuit package.

22. The computer device of claim 20, wherein the passive electrical component comprises at least one of a resistor, capacitor, power component, or through mold via (TMV).

23. The computer device of claim 22, wherein the passive electrical component is electrically coupled to the bottom circuit package.

24. The computer device of claim 22, wherein the bottom circuit package comprises a bottom circuit package substrate and wherein the TMV comprises vertical walls perpendicular to the top circuit package substrate and the bottom circuit package substrate.

25. The computer device of claim 20, wherein the second ball grid array forms more electrical contacts between the interface side of the bottom circuit package substrate and the motherboard than the first ball grid array forms between the interface side of the top circuit package substrate and the bottom circuit package.