THERMALLY CONSCIOUS STANDARD CELLS

• US 20190103394A1
• Filed: 09/29/2017
• Published: 04/04/2019
• Est. Priority Date: 09/29/2017
• Status: Active Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Andrews, Sean Charles, Lee, Yong Ju
• Application Number:
  US15/719,877
• Publication Number:
  US 20190103394A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 23/3731 Ceramic materials or glass H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/3732 Diamonds
• CPC Class Codes: H01L 23/3737 Organic materials with or without a thermoconductive filler
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 27/0211 adapted for requirements of temperature
• CPC Class Codes: H01L 27/11807 CMOS gate arrays

Abstract

In certain aspects, an integrated circuit comprises a first standard cell having a height equal to a cell height, wherein the first standard cell comprises a first dielectric material in a first layer. The integrated circuit comprises a second standard cell having a height equal to the cell height and aligning with the first standard cell, wherein the second standard cell comprises the first dielectric material in the first layer. The integrated circuit further comprises a first thermal cell having a height equal to the cell height and aligning with and abutting to both the first standard cell and the second standard cell; and wherein the first thermal cell comprises a second dielectric material in the first layer having a higher thermal conductivity than that of the first dielectric material.

Claims

1. An integrated circuit, comprising:

A first standard cell having a height equal to a cell height, wherein the first standard cell comprises a first dielectric material in a first layer;

A second standard cell having a height equal to the cell height and aligning with the first standard cell, wherein the second standard cell comprises the first dielectric material in the first layer; and

A first thermal cell having a height equal to the cell height and aligning with and abutting to both the first standard cell and the second standard cell, wherein the first thermal cell comprises a second dielectric material in the first layer having a higher thermal conductivity than that of the first dielectric material.

2. The integrated circuit of claim 1, wherein the second dielectric material comprises one of AlN, BN, polycrystalline diamond, or their alloys.

3. The integrated circuit of claim 1, wherein the first standard cell further comprises a third dielectric material in a second layer;

the second standard cell further comprises the third dielectric material in the second layer; and

the first thermal cell further comprises a fourth dielectric material in the second layer having a higher thermal conductivity than that of the third dielectric material.

4. The integrated circuit of claim 3, wherein the third dielectric material is different to the first dielectric material;

and wherein the fourth dielectric material is same as the second dielectric material.

5. The integrated circuit of claim 4, wherein both the second and the fourth materials comprise one of AlN, BN, polycrystalline diamond, or their alloys.

6. The integrated circuit of claim 1, wherein the first standard cell further comprises a third dielectric material in a second layer;

the second standard cell further comprises the third dielectric material in the second layer; and

the first layer and the second layer of the first thermal cell comprise the second dielectric material deposited in the same one or more steps.

7. The integrated circuit of claim 1, wherein an Nwell for the first standard cell, an Nwell for the second standard cell, and an Nwell for the first thermal cell are abutted and merged into one large nwell.

8. The integrated circuit of claim 1, wherein a power rail for the first standard cells, a power rail for the second standard cell, and a power rail for the first thermal cell are abutted to form a common power rail arranged along a straight line.

9. The integrated circuit of claim 1 further comprising a second thermal cell abutted to the first standard cell, wherein the second thermal cell has a height equal to the cell height aligning with the first standard cell, the second standard cell, and the first thermal cell.

10. The integrated circuit of claim 9, wherein the second thermal cell is same as the first thermal cell.

11. The integrated circuit of claim 1, wherein the first thermal cell further comprises a heat storage material.

12. The integrated circuit of claim 11, wherein the heat storage material is a solid/solid phase change material (PCM).

13. The integrated circuit of claim 11, wherein the heat storage material is surrounded by the second dielectric material.

14. A method, comprising:

Placing a first standard cell in a circuit row, wherein the first standard cell has height equal to a cell height and comprises a first dielectric material in a first layer;

Placing a second standard cell in the circuit row, wherein the second standard cell has a height equal to the cell height and comprises the first dielectric material in the first layer; and

Placing a first thermal cell in the circuit row abutted to both the first standard cell and the second standard cell, wherein the first thermal cell has a height equal to the cell height, wherein the first standard cell, the second standard cell, and the first thermal cell are aligned; and

wherein the first thermal cell comprises a second dielectric material in the first layer having a higher thermal conductivity than that of the first dielectric material.

15. The method of claim 14, wherein the second dielectric material comprises one of AlN, BN, polycrystalline diamond, or their alloys.

16. The method of claim 14, wherein an Nwell for the first standard cell, an Nwell for the second standard cell, and an Nwell for the first thermal cell are abutted and merged into one large nwell.

17. The method of claim 14, wherein a power rail for the first standard cells, a power rail for the second standard cell, and a power rail for the first thermal cell are abutted to form a common power rail arranged along a straight line.

18. The method of claim 14 further comprising placing a second thermal cell abutted to the first standard cell, wherein the second thermal cell has a height equal to the cell height and is aligned with the first standard cell, the second standard cell, and the first thermal cell.

19. The method of claim 18, wherein the second thermal cell is same as the first thermal cell.

20. The method of claim 14, wherein the first thermal cell further comprises a heat storage material.

21. The method of claim 20, wherein the heat storage material is a solid/solid phase change material (PCM).

22. The method of claim 20, wherein the heat storage material is surrounded by the second dielectric material.