SYSTEMS AND METHODS FOR GRANULAR NON-VOLATILE MEMORY HEALTH VISIBILITY TO A HOST

• US 20190107960A1
• Filed: 10/06/2017
• Published: 04/11/2019
• Est. Priority Date: 10/06/2017
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: SANKARANARAYANAN, Vadhiraj, KAKARLA, Krishna Pradyumna, RAO, Balaji Bapu Gururaja, JREIJ, Elie Antoun
• Granted Patent: US 10,732,859 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/1428 with loss of hardware functionality
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

In accordance with embodiments of the present disclosure, an information handling system may include a processor and a memory system communicatively coupled to the processor. The memory system may include one or more persistent memory modules, each of the one or more persistent memory modules comprising a volatile memory and a non-volatile memory and one or more health registers accessible to a host system executing on the processor, the health registers storing health information indicating, for each of a plurality of ranks of the volatile memory, whether the memory system can reliably perform a save operation to a portion of non-volatile memory mapped to volatile memory of the rank.

Claims

1. An information handling system comprising:

a processor; and

a memory system communicatively coupled to the processor, the memory system comprising;

one or more persistent memory modules, each of the one or more persistent memory modules comprising a volatile memory and a non-volatile memory; and

one or more health registers accessible to a host system executing on the processor, the one or more health registers configured to store health information indicating, for each of a plurality of ranks of the volatile memory, whether the memory system can reliably perform a save operation to a portion of non-volatile memory mapped to volatile memory of the rank.

2. The information handling system of claim 1, wherein the health information includes information regarding correctable restore errors.

3. The information handling system of claim 2, wherein the health information includes a severity for each correctable restore error.

4. The information handling system of claim 1, wherein the health information includes information regarding the usage of the volatile memory or the non-volatile memory within each rank.

5. The information handling system of claim 1, wherein the health information includes runtime updates regarding memory media health based on diagnostic tests.

6. The information handling system of claim 1, wherein the host system executing on the processor is further configured to:

read rank-level health information from the one or more health registers; and

allocate data to physical addresses of the memory system based on the rank-level health information.

7. The information handling system of claim 6, wherein allocating data to physical addresses comprises mapping of virtual memory addresses to physical memory addresses based on the health information.

8. A method comprising, in a memory system comprising one or more persistent memory modules, each of the one or more persistent memory modules comprising a volatile memory and a non-volatile memory:

storing health information in one or more health registers of a memory system, the health information indicating, for each of a plurality of ranks of the volatile memory, whether the memory system can reliably perform a save operation to a portion of non-volatile memory mapped to volatile memory of the rank, such that the health information is accessible to a host system executing on a processor communicatively coupled to the memory system.

9. The method of claim 8, wherein the health information includes information regarding correctable restore errors.

10. The method of claim 9, wherein the health information includes a severity for each correctable restore error.

11. The method of claim 8, wherein the health information includes information regarding the usage of the volatile memory or the non-volatile memory within each rank.

12. The method of claim 8, wherein the health information includes runtime updates regarding memory media health based on diagnostic tests.

13. The method of claim 8, further comprising, by the host system executing on the processor communicatively coupled to the memory system:

reading rank-level health information from the one or more health registers; and

allocating data to physical addresses of the memory system based on the rank-level health information.

14. The method of claim 13, wherein allocating data to physical addresses comprises mapping of virtual memory addresses to physical memory addresses based on the health information.

15. A memory system comprising:

one or more persistent memory modules, each of the one or more persistent memory modules comprising a volatile memory and a non-volatile memory; and

one or more health registers accessible to a host system, the one or more health registers configured to store health information indicating, for each of a plurality of ranks of the volatile memory, whether the memory system can reliably perform a save operation to a portion of non-volatile memory mapped to volatile memory of the rank.

16. The memory system of claim 15, wherein level health information includes information regarding correctable restore errors.

17. The memory system of claim 16, wherein the health information includes a severity for each correctable restore error.

18. The memory system of claim 15, wherein the health information includes information regarding the usage of the volatile memory or the non-volatile memory within the rank.

19. The memory system of claim 15, wherein the health information includes runtime updates regarding memory media health based on diagnostic tests.

20. The memory system of claim 15, wherein the host system is further configured to:

read rank-level health information from the one or more health registers; and

allocate data to physical addresses of the memory system based on the rank-level health information.