METHOD OF FABRICATING DRAM

• US 20190109139A1
• Filed: 08/02/2018
• Published: 04/11/2019
• Est. Priority Date: 10/10/2017
• Status: Active Grant

• Current Assignee: Fujian Jinhua Integrated Circuit Co., Ltd., United Microelectronics Corporation
• Original Assignee: Fujian Jinhua Integrated Circuit Co., Ltd., United Microelectronics Corporation
• Inventors: Wu, Tzu-Chin, Liu, Chao-An, Chang, Ching-Hsiang, Chen, Yi-Wei
• Granted Patent: US 10,446,559 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A method of fabricating a DRAM includes providing a substrate. Later, a first mask layer is formed to cover the substrate. The first mask layer includes a hydrogen-containing silicon nitride layer and a silicon oxide layer. The hydrogen-containing silicon nitride layer has the chemical formula: Si_xN_yH_z, wherein x is between 4 and 8, y is between 3.5 and 9.5, and z equals 1. After that, the first mask layer is patterned to form a first patterned mask layer. Next, the substrate is etched by taking the first patterned mask layer as a mask to form a word line trench. Subsequently, the first patterned mask layer is removed entirely. Finally, a word line is formed in the word line trench.

Claims

1. A method of fabricating a DRAM, comprising:

providing a substrate; and

forming a first mask layer, wherein the steps of forming the first mask layer comprise;

forming a hydrogen-containing silicon nitride layer to cover the substrate, and forming a silicon oxide layer to cover and contact the hydrogen-containing silicon nitride layer, wherein the hydrogen-containing silicon nitride layer has the chemical formula;

Si_xN_yH_z, wherein x is between 4 and 8, y is between 3.5 and 9.5, and z equals 1;

patterning the first mask layer to form a first patterned mask layer;

etching the substrate by taking the first patterned mask layer as a first mask to form a word line trench;

removing the first patterned mask layer entirely; and

forming a word line in the word line trench.

2. The method of fabricating a DRAM of claim 1, wherein the substrate comprises a semiconductor substrate and a second mask layer covering the semiconductor substrate.

3. The method of fabricating a DRAM of claim 2, wherein the fabricating steps of the word line comprise:

etching the second mask layer to forma second patterned mask layer by taking the first patterned mask layer as a second mask;

removing the first patterned mask layer;

etching the semiconductor substrate to form the word line trench by taking the second patterned mask layer as a third mask; and

removing the second patterned mask layer.

4. The method of fabricating a DRAM of claim 1, further comprising:

forming a doping region in the substrate before forming the first mask layer;

forming a capacitor plug to contact the doping region after forming the word line; and

forming a capacitor on the substrate to complete the DRAM after forming the word line, wherein the capacitor electrically connects to the word line through the doping region and the capacitor plug.

5. The method of fabricating a DRAM of claim 1, wherein the hydrogen-containing silicon nitride layer is formed by a deposition process, and the deposition process comprises:

forming the hydrogen-containing silicon nitride layer by using silane and ammonia as precursors, wherein a flow rate of the silane is between 22.5 and 27.5 SCCM, and a flow rate of the ammonia is between 45 and 55 SCCM.

6. The method of fabricating a DRAM of claim 5, wherein an operation temperature of the deposition process is between 360 and 440 degrees Celsius, an operation pressure is between 5.4 and 6.6 torrs, and an operation power is between 72 and 88 watts.