SM4 ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

• US 20190109704A1
• Filed: 09/29/2018
• Published: 04/11/2019
• Est. Priority Date: 07/22/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: GUERON, Shay, KRASNOV, Vlad
• Granted Patent: US 10,447,468 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30156 Special purpose encoding of instructions, e.g. Gray coding
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/24 Key scheduling, i.e. generating round keys or sub-keys for block encryption
• CPC Class Codes: H04L 2209/80 Wireless network architectures or network communication protocols for wireless network security H04W12/00
• CPC Class Codes: H04L 9/0625 with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0637 Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]

Abstract

A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.

Claims

1. A system comprising:

a system memory; and

a processor coupled to the system memory, the processor comprising;

a data cache;

a data translation lookaside buffer (TLB) coupled to the data cache;

a branch prediction unit;

an instruction cache;

an instruction TLB coupled to the instruction cache;

an instruction fetch unit to fetch instructions, including an instruction;

a level 2 (L2) cache coupled to the data cache, and coupled to the instruction cache;

a plurality of registers to store single instruction, multiple data (SIMD) data, including a first register, and a second register, the first register to store a first source data that includes four source data elements to be encrypted with an SM4 cryptographic algorithm, the second register to store a second source data that includes four round keys, wherein the plurality of registers are dynamically allocated using register renaming;

a decode unit to decode the instruction, the instruction having a first field to specify the first register, and a second field to specify the second register; and

an execution unit coupled to the decode unit, and coupled to the plurality of registers, the execution unit, in response to the decode of the instruction, to generate and store a result in the first register, the result to include four result data elements that include the first source data encrypted by four corresponding encryption rounds of the SM4 cryptographic algorithm, wherein the execution unit is to generate each of the four result data elements to be consistent with an evaluation of a linear substitution function with a value for the corresponding encryption round, which is equal to the value logically XOR'"'"'d with the value rotated left by two bits logically XOR'"'"'d with the value rotated left by ten bits logically XOR'"'"'d with the value rotated left by eighteen bits logically XOR'"'"'d with the value rotated left by twenty-four bits.

2. The system of claim 1, wherein the first source data is to include a first data element in bits [31:

0], a second data element in bits [63;

32], a third data element in bits [95;

64], and a fourth data element in bits [127;

96], wherein the second source data is to include a first round key in bits [31;

0], a second round key in bits [63;

32], a third round key in bits [95;

64], and a fourth round key in bits [127;

96], and wherein the result is to include a first result data element in bits [31;

0] that is equal to the first data element logically exclusive OR'"'"'d (XOR'"'"'d) with a first output of a function evaluated with a first input, the first input equal to the second data element logically XOR'"'"'d with the third data element logically XOR'"'"'d with the fourth data element logically XOR'"'"'d with the first round key, the first output equal to a first value, which is equal to a substitution box applied to the first input, logically XOR'"'"'d with the first value rotated left by two bits logically XOR'"'"'d with the first value rotated left by ten bits logically XOR'"'"'d with the first value rotated left by eighteen bits logically XOR'"'"'d with the first value rotated left by twenty-four bits.

3. The system of claim 2, wherein the result is further to include:

a second result data element in bits [63;

32] that is equal to the second data element logically XOR'"'"'d with a second output of the function evaluated with a second input, the second input equal to the third data element logically XOR'"'"'d with the fourth data element logically XOR'"'"'d with the first result data element logically XOR'"'"'d with the second round key, the second output equal to a second value of the substitution box applied to the second input logically XOR'"'"'d with the second value rotated left by two bits logically XOR'"'"'d with the second value rotated left by ten bits logically XOR'"'"'d with the second value rotated left by eighteen bits logically XOR'"'"'d with the second value rotated left by twenty-four bits;

a third result data element in bits [95;

64] that is equal to the third data element logically XOR'"'"'d with a third output of the function evaluated with a third input, the third input equal to the fourth data element logically XOR'"'"'d with the first result data element logically XOR'"'"'d with the second result data element logically XOR'"'"'d with the third round key, the third output equal to a third value of the substitution box applied to the third input logically XOR'"'"'d with the third value rotated left by two bits logically XOR'"'"'d with the third value rotated left by ten bits logically XOR'"'"'d with the third value rotated left by eighteen bits logically XOR'"'"'d with the third value rotated left by twenty-four bits; and

a fourth result data element in bits [127;

96] that is equal to the fourth data element logically XOR'"'"'d with a fourth output of the function evaluated with a fourth input, the fourth input equal to the first result data element logically XOR'"'"'d with the second result data element logically XOR'"'"'d with the third result data element logically XOR'"'"'d with the fourth round key, the fourth output equal to a fourth value of the substitution box applied to the fourth input logically XOR'"'"'d with the fourth value rotated left by two bits logically XOR'"'"'d with the fourth value rotated left by ten bits logically XOR'"'"'d with the fourth value rotated left by eighteen bits logically XOR'"'"'d with the fourth value rotated left by twenty-four bits.

4. The system of claim 1, wherein the result is 128-bits and is to include:

a first result data element for an encryption round i+4 in bits [31;

0];

a second result data element for an encryption round i+5 in bits [63;

32];

a third result data element for an encryption round i+6 in bits [95;

64]; and

a fourth result data element for an encryption round i+7 in bits [127;

96].

5. The system of claim 4, wherein the second source data is 128-bits and is to have:

a first round key for an encryption round i in bits [31;

0];

a second round key for an encryption round i+1 in bits [63;

32];

a third round key for an encryption round i+2 in bits [95;

64]; and

a fourth round key for an encryption round i+3 in bits [127;

96].

6. The system of claim 1, wherein the execution unit, in response to the decode of the instruction, is to generate each of the four result data elements by performing a mixer substitution for the corresponding encryption round, the mixer substitution including a linear substitution on a result of a non-linear substitution.

7. The system of claim 1, wherein the processor is a reduced instruction set computing (RISC) processor.

8. The system of claim 1, wherein the decode unit is also to decode a second instruction, the second instruction having a third field to specify a third register of the plurality of registers, a fourth field to specify a fourth register of the plurality of registers, and a fifth field to specify a destination register of the plurality of registers, the third register to store a third source data that includes four round keys corresponding to four prior key expansion rounds of the SM4 cryptographic algorithm, the fourth register to store a fourth source data that includes four key generation constants, and wherein the processor, in response to the decode of the second instruction, is to generate and store a second result in the destination register, the second result to include four round keys corresponding to four sequential key expansion rounds of the SM4 cryptographic algorithm that sequentially follow the four prior key expansion rounds.

9. The system of claim 1, further comprising audio I/O coupled to the processor.

10. The system of claim 1, further comprising a communication device coupled to the processor.

11. The system of claim 1, further comprising an I/O device coupled to the processor.

12. The system of claim 1, further comprising a mass storage device coupled to the processor.

13. The system of claim 12, wherein the mass storage device comprises a disk drive.

14. The system of claim 1, further comprising a Peripheral Component Interconnect (PCI) Express bus coupled to the processor.

15. The system of claim 1, further comprising a graphics processor coupled to the processor.

16. The system of claim 1, wherein the system memory comprises dynamic random access memory (DRAM).

17. A system comprising:

a system memory; and

a processor coupled to the system memory, the processor comprising;

a plurality of registers to store single instruction, multiple data (SIMD) data, including a first register, and a second register, the first register to store a first source data that includes four source data elements to be encrypted with an SM4 cryptographic algorithm, the second register to store a second source data that includes four round keys, wherein the plurality of registers are dynamically allocated using register renaming;

a decode unit to decode an instruction, the instruction having a first field to specify the first register, and a second field to specify the second register; and

an execution unit coupled to the decode unit, and coupled to the plurality of registers, the execution unit, in response to the decode of the instruction, to generate and store a result in the first register, the result to include four result data elements that include the first source data encrypted by four corresponding encryption rounds of the SM4 cryptographic algorithm, wherein the execution unit is to generate each of the four result data elements to be consistent with an evaluation of a linear substitution function with a value for the corresponding encryption round, which is equal to the value logically XOR'"'"'d with the value rotated left by two bits logically XOR'"'"'d with the value rotated left by ten bits logically XOR'"'"'d with the value rotated left by eighteen bits logically XOR'"'"'d with the value rotated left by twenty-four bits.

18. The system of claim 17, wherein the processor is a reduced instruction set computing (RISC) processor.

19. The system of claim 17, wherein the decode unit is also to decode a second instruction, the second instruction having a third field to specify a third register of the plurality of registers, a fourth field to specify a fourth register of the plurality of registers, and a fifth field to specify a destination register of the plurality of registers, the third register to store a third source data that includes four round keys corresponding to four prior key expansion rounds of the SM4 cryptographic algorithm, the fourth register to store a fourth source data that includes four key generation constants, and wherein the processor, in response to the decode of the second instruction, is to generate and store a second result in the destination register, the second result to include four round keys corresponding to four sequential key expansion rounds of the SM4 cryptographic algorithm that sequentially follow the four prior key expansion rounds.

20. The system of claim 17, wherein the second source data is 128-bits and is to have:

a first round key for an encryption round i in bits [31;

0];

a second round key for an encryption round i+1 in bits [63;

32];

a third round key for an encryption round i+2 in bits [95;

64]; and

a fourth round key for an encryption round i+3 in bits [127;

96].

21. The system of claim 17, wherein the result is 128-bits and is to include:

a first result data element for an encryption round i+4 in bits [31;

0];

a second result data element for an encryption round i+5 in bits [63;

32];

a third result data element for an encryption round i+6 in bits [95;

64]; and

a fourth result data element for an encryption round i+7 in bits [127;

96].

22. The system of claim 17, wherein the execution unit, in response to the decode of the instruction, is to generate each of the four result data elements by performing a mixer substitution for the corresponding encryption round, the mixer substitution including a linear substitution on a result of a non-linear substitution, and wherein the processor further comprises:

a data cache;

a data translation lookaside buffer (TLB) coupled to the data cache;

a branch prediction unit;

an instruction cache;

an instruction TLB coupled to the instruction cache;

an instruction fetch unit to fetch instructions, including the instruction; and

a level 2 (L2) cache coupled to the data cache, and coupled to the instruction cache.

23. The system of claim 17, wherein the first source data is to include a first data element in bits [31:

0], a second data element in bits [63;

32], a third data element in bits [95;

64], and a fourth data element in bits [127;

96], wherein the second source data is to include a first round key in bits [31;

0], a second round key in bits [63;

32], a third round key in bits [95;

64], and a fourth round key in bits [127;

96], and wherein the result is to include a first result data element in bits [31;

0] that is equal to the first data element logically exclusive OR'"'"'d (XOR'"'"'d) with a first output of a function evaluated with a first input, the first input equal to the second data element logically XOR'"'"'d with the third data element logically XOR'"'"'d with the fourth data element logically XOR'"'"'d with the first round key, the first output equal to a first value, which is equal to a substitution box applied to the first input, logically XOR'"'"'d with the first value rotated left by two bits logically XOR'"'"'d with the first value rotated left by ten bits logically XOR'"'"'d with the first value rotated left by eighteen bits logically XOR'"'"'d with the first value rotated left by twenty-four bits.

24. The system of claim 23, wherein the result is further to include:

a second result data element in bits [63;

32] that is equal to the second data element logically XOR'"'"'d with a second output of the function evaluated with a second input, the second input equal to the third data element logically XOR'"'"'d with the fourth data element logically XOR'"'"'d with the first result data element logically XOR'"'"'d with the second round key, the second output equal to a second value of the substitution box applied to the second input logically XOR'"'"'d with the second value rotated left by two bits logically XOR'"'"'d with the second value rotated left by ten bits logically XOR'"'"'d with the second value rotated left by eighteen bits logically XOR'"'"'d with the second value rotated left by twenty-four bits;

a third result data element in bits [95;

64] that is equal to the third data element logically XOR'"'"'d with a third output of the function evaluated with a third input, the third input equal to the fourth data element logically XOR'"'"'d with the first result data element logically XOR'"'"'d with the second result data element logically XOR'"'"'d with the third round key, the third output equal to a third value of the substitution box applied to the third input logically XOR'"'"'d with the third value rotated left by two bits logically XOR'"'"'d with the third value rotated left by ten bits logically XOR'"'"'d with the third value rotated left by eighteen bits logically XOR'"'"'d with the third value rotated left by twenty-four bits; and

a fourth result data element in bits [127;

96] that is equal to the fourth data element logically XOR'"'"'d with a fourth output of the function evaluated with a fourth input, the fourth input equal to the first result data element logically XOR'"'"'d with the second result data element logically XOR'"'"'d with the third result data element logically XOR'"'"'d with the fourth round key, the fourth output equal to a fourth value of the substitution box applied to the fourth input logically XOR'"'"'d with the fourth value rotated left by two bits logically XOR'"'"'d with the fourth value rotated left by ten bits logically XOR'"'"'d with the fourth value rotated left by eighteen bits logically XOR'"'"'d with the fourth value rotated left by twenty-four bits.

25. The system of claim 17, wherein the system memory comprises dynamic random access memory (DRAM), and further comprising a mass storage device coupled to the processor.

26. The system of claim 25, wherein the mass storage device comprises a disk drive.

27. The system of claim 17, further comprising a Peripheral Component Interconnect (PCI) Express bus coupled to the processor.

28. The system of claim 17, further comprising a graphics processor coupled to the processor.

29. The system of claim 17, further comprising a communication device coupled to the processor.

30. A method comprising:

storing data in a system memory;

dynamically allocating a plurality of registers that are used to store single instruction, multiple data (SIMD) data using register renaming;

receiving a first source data including four source data elements, which are to be encrypted with an SM4 cryptographic algorithm, from a first register of the plurality of registers;

receiving a second source data including four round keys from a second register of the plurality of registers;

decoding an instruction having a first field specifying the first register, and a second field specifying the second register;

generating a result, in response to the decode of the instruction, the result including four result data elements that include the first source data encrypted by four corresponding encryption rounds of the SM4 cryptographic algorithm, each of the four result data elements is generated to be consistent with an evaluation of a linear substitution function with a value for the corresponding encryption round, which is equal to the value logically XOR'"'"'d with the value rotated left by two bits logically XOR'"'"'d with the value rotated left by ten bits logically XOR'"'"'d with the value rotated left by eighteen bits logically XOR'"'"'d with the value rotated left by twenty-four bits; and

storing the result in the first register in response to the decode of the instruction.

31. The method of claim 30, wherein said receiving the second source data comprises receiving a first round key for an encryption round i from bits [31:

0] of the second register, receiving a second round key for an encryption round i+1 from bits [63;

32] of the second register, receiving a third round key for an encryption round i+2 from bits [95;

64] of the second register, and receiving a fourth round key for an encryption round i+3 from bits [127;

96] of the second register, and wherein said storing the result in the first register comprises storing a first result data element for an encryption round i+4 in bits [31;

0] of the first register, storing a second result data element for an encryption round i+5 in bits [63;

32] of the first register, storing a third result data element for an encryption round i+6 in bits [95;

64] of the first register, and storing a fourth result data element for an encryption round i+7 in bits [127;

96] of the first register.

32. An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing instructions, wherein the instructions, if executed by a machine, are to cause the machine to perform operations comprising to:

store data in a system memory;

receive a first source data including four source data elements, which are to be encrypted with an SM4 cryptographic algorithm, from a first register of a plurality of registers that are used to store single instruction, multiple data (SIMD) data;

receive a second source data including four round keys from a second register of the plurality of registers;

generate a result that is to include four result data elements that are to include the first source data encrypted by four corresponding encryption rounds of the SM4 cryptographic algorithm, wherein each of the four result data elements is to be generated to be consistent with an evaluation of a linear substitution function with a value for the corresponding encryption round, which is equal to the value logically XOR'"'"'d with the value rotated left by two bits logically XOR'"'"'d with the value rotated left by ten bits logically XOR'"'"'d with the value rotated left by eighteen bits logically XOR'"'"'d with the value rotated left by twenty-four bits; and

store the result in the first register.

33. The article of manufacture of claim 32, wherein the instructions further comprise instructions that, if executed by the machine, are to cause the machine to perform operations comprising to:

receive a first round key for an encryption round i from bits [31;

0] of the second register;

receive a second round key for an encryption round i+1 from bits [63;

32] of the second register;

receive a third round key for an encryption round i+2 from bits [95;

64] of the second register;

receive a fourth round key for an encryption round i+3 from bits [127;

96] of the second register;

store a first result data element for an encryption round i+4 in bits [31;

0] of the first register;

store a second result data element for an encryption round i+5 in bits [63;

32] of the first register;

store a third result data element for an encryption round i+6 in bits [95;

64] of the first register; and

store a fourth result data element for an encryption round i+7 in bits [127;

96] of the first register.