Processor Using Memory-Based Computation

• US 20190114170A1
• Filed: 11/12/2018
• Published: 04/18/2019
• Est. Priority Date: 02/13/2016
• Status: Abandoned Application

• Current Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: ZHANG, Guobiao
• Application Number:
  US16/188,265
• Publication Number:
  US 20190114170A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/03 working, at least partly, by table look-up G06F1/025 takes precedence
• CPC Class Codes: G06F 1/0356 by using two or more smaller tables, e.g. addressed by parts of the argument
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 15/785 with decentralized control, e.g. smart memories
• CPC Class Codes: G06F 17/11 for solving equations , e.g. nonlinear equations, general mathematical optimization problems optimization specially adapted for a specific administrative, business or logistic context G06Q10/04
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 7/00 Methods or arrangements for processing data by operating upon the order or content of the data handled logic circuits H03K19/00
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• CPC Class Codes: H10B 20/34 Source electrode or drain electrode programmed

Abstract

Instead of logic-based computation (LBC), the preferred processor disclosed in the present invention uses memory-based computation (MBC). It comprises an array of computing elements, with each computing element comprising a memory array on a memory level for storing a look-up table (LUT) and an arithmetic logic circuit (ALC) on a logic level for performing arithmetic operations on selected LUT data. The memory level and the logic level are different physical levels.

Claims

1-20. -20. (canceled)

21. A processor for implementing a mathematical function, comprising:

at least first and second memory arrays on a memory level, wherein said first memory array stores at least a first portion of a first look-up table (LUT) for a first non-arithmetic function; and

, said second memory array stores at least a second portion of a second LUT for a second non-arithmetic function;

at least an arithmetic logic circuit (ALC) on a logic level for performing at least an arithmetic operation on selected data from said first LUT or said second LUT, wherein said logic level is a different physical level than said memory level; and

means for communicatively coupling said first or second memory array with said ALC;

wherein said mathematical function is a combination of at least said first and second non-arithmetic functions.

22. The processor according to claim 21, wherein each of said first and second non-arithmetic functions is a mathematical function whose operations are more than arithmetic operations performable by said ALC.

23. The processor according to claim 22, wherein said arithmetic operations performable by said ALC consist of addition, subtraction and multiplication.

24. The processor according to claim 21, wherein said first memory array or said second memory array at least partially overlaps with said ALC.

25. The processor according to claim 21, wherein said first LUT includes the functional values of said mathematical function;

and, said second LUT includes the derivative values of said mathematical function.

26. The processor according to claim 21, wherein said mathematical function is a composite function of said first and second non-arithmetic functions.

27. The processor according to claim 21, wherein said first non-arithmetic function has a first independent variable;

said second non-arithmetic function has a second independent variable; and

, said mathematical function has at least said first and second independent variables.

28. The processor according to claim 21, further comprising a single semiconductor substrate, wherein said ALC is disposed on said semiconductor substrate;

said first and second memory arrays are three-dimensional memory (3D-M) arrays stacked above said ALC; and

, said ALC and said 3D-M arrays are communicatively coupled by a plurality of contact vias.

29. The processor according to claim 21, further comprising a single semiconductor substrate with first and second sides, wherein said ALC is disposed on said first side;

said first and second memory arrays are disposed on said second side; and

, said first and second sides are coupled by a plurality of through-substrate vias through said semiconductor substrate.

30. The processor according to claim 21, wherein said ALC disposed on at least a logic die;

said first and second memory arrays are disposed on at least a memory die; and

, said logic die and said memory die are located in a same package.

31. The processor according to claim 21, wherein said processor is a micro-controller, a controller, a central processing unit (CPU), a digital signal processor (DSP), a graphic processing unit (GPU), a network-security processor, an encryption/decryption processor, an encoding/decoding processor, a neural-network processor, or an artificial intelligence (AI) processor.

32. A processor for implementing a mathematical function, comprising:

at least a memory array on a memory level for storing at least a portion of a look-up table (LUT) for a non-arithmetic function;

at least an arithmetic logic circuit (ALC) on a logic level for performing at least an arithmetic operation on selected data from said LUT; and

means for communicatively coupling said memory array and said ALC,

wherein said memory level and said logic level are different physical levels.

33. The processor according to claim 32, wherein said non-arithmetic function is a mathematical function whose operations are more than arithmetic operations performable by said ALC.

34. The processor according to claim 33, wherein said arithmetic operations performable by said ALC consist of addition, subtraction and multiplication.

35. The processor according to claim 32, wherein said memory array at least partially overlaps with said ALC.

36. The processor according to claim 32, wherein said LUT includes the functional values or the derivative values of said mathematical function.

37. The processor according to claim 32, further comprising a single semiconductor substrate, wherein said ALC is disposed on said semiconductor substrate;

said memory array is a three-dimensional memory (3D-M) array stacked above said ALC; and

, said ALC and said 3D-M array are communicatively coupled by a plurality of contact vias.

38. The processor according to claim 32, further comprising a single semiconductor substrate with first and second sides, wherein said ALC is disposed on said first side;

said memory array is disposed on said second side; and

, said first and second sides are coupled by a plurality of through-substrate vias through said semiconductor substrate.

39. The processor according to claim 32, wherein said ALC disposed on at least a logic die;

said memory array is disposed on at least a memory die; and

, said logic die and said memory die are located in a same package.

40. The processor according to claim 32, wherein said processor is a micro-controller, a controller, a central processing unit (CPU), a digital signal processor (DSP), a graphic processing unit (GPU), a network-security processor, an encryption/decryption processor, an encoding/decoding processor, a neural-network processor, or an artificial intelligence (AI) processor.