NON-VOLATILE MEMORY

• US 20190115076A1
• Filed: 05/25/2018
• Published: 04/18/2019
• Est. Priority Date: 10/13/2017
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: CHEN, Chih-Hsin, Wang, Shih-Chen
• Granted Patent: US 10,642,579 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H10B 41/10 characterised by the top-view layout

Abstract

A non-volatile memory includes a memory cell. A storage element of the memory cell has following structures. A first floating gate transistor includes a first floating gate, a first source/drain terminal and a second source/drain terminal. A second floating gate transistor includes the first floating gate, a third source/drain terminal and a fourth source/drain terminal. A third floating gate transistor includes a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal. A fourth floating gate transistor includes the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal. The first and third source/drain terminals are connected with a first terminal of the storage element. The second and fifth source/drain terminals are connected with each other. The fourth and seventh source/drain terminals are connected with each other. The sixth and eighth source/drain terminals are connected with a second terminal of the storage element.

Claims

1. A non-volatile memory comprising a memory cell, the memory cell comprising a storage element, the storage element comprising p×

q floating gate transistors,

wherein the q floating gate transistors in each row are serially connected between a first terminal and a second terminal of the storage element, and

wherein the x-th floating gate transistors in each row share an x-th floating gate, wherein x is an integer, and 1≤

x≤

q.

2. The non-volatile memory as claimed in claim 1, wherein the storage element comprises:

a first floating gate transistor comprising a first floating gate, a first source/drain terminal and a second source/drain terminal;

a second floating gate transistor comprising the first floating gate, a third source/drain terminal and a fourth source/drain terminal;

a third floating gate transistor comprising a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal; and

a fourth floating gate transistor comprising the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal,

wherein the first source/drain terminal and the third source/drain terminal are connected with the first terminal of the storage element, the second source/drain terminal is connected with the fifth source/drain terminal, the fourth source/drain terminal is connected with the seventh source/drain terminal, and the sixth source/drain terminal and the eighth source/drain terminal are connected with the second terminal of the storage element.

3. The non-volatile memory as claimed in claim 2, wherein the first floating gate transistor has a first channel length, the second floating gate transistor has a second channel length, the third floating gate transistor has a third channel length, and the fourth floating gate transistor has a fourth channel length, wherein the first channel length is larger than the third channel length, and the fourth channel length is larger than the second channel length.

4. The non-volatile memory as claimed in claim 2, wherein the memory cell further comprises:

a control transistor comprising a first gate, a ninth source/drain terminal and a tenth source/drain terminal, wherein the first gate is connected with a word line, the ninth source/drain terminal is connected with a bit line, and the tenth source/drain terminal is connected with the second terminal of the storage element.

5. The non-volatile memory as claimed in claim 2, wherein the memory cell further comprises:

a select transistor comprising a second gate, an eleventh source/drain terminal and a twelfth source/drain terminal, wherein the second gate is connected with a select line, the eleventh source/drain terminal is connected with a source line, and the twelfth source/drain terminal is connected with the first terminal of the storage element.

6. The non-volatile memory as claimed in claim 1, wherein the memory cell further comprises q capacitors, and the x-th capacitor is connected between the x-th floating gate and a control line.

7. The non-volatile memory as claimed in claim 1, wherein the memory cell further comprises q capacitors, and the x-th capacitor is connected between the x-th floating gate and an erase line.

8. A non-volatile memory comprising a memory cell, the memory cell comprising a storage element, the storage element comprising p×

q floating gate transistors,

wherein the q floating gate transistors in the y-th row are serially connected between a (2y−

1)-th terminal and a (2y)-th terminal of the storage element, wherein y is an integer, and 1≤

y≤

p,

wherein the x-th floating gate transistors in each row share an x-th floating gate, wherein x is an integer, and 1≤

x≤

q.

9. The non-volatile memory as claimed in claim 8, wherein the storage element comprising:

a first floating gate transistor comprising a first floating gate, a first source/drain terminal and a second source/drain terminal;

a second floating gate transistor comprising the first floating gate, a third source/drain terminal and a fourth source/drain terminal;

a third floating gate transistor comprising a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal; and

a fourth floating gate transistor comprising the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal,

wherein the first source/drain terminal is connected with a first terminal of the storage element, the third source/drain terminal is connected with a second terminal of the storage element, the second source/drain terminal is connected with the fifth source/drain terminal, the fourth source/drain terminal is connected with the seventh source/drain terminal, the sixth source/drain terminal is connected with a third terminal of the storage element, and the eighth source/drain terminal is connected with a fourth terminal of the storage element.

10. The non-volatile memory as claimed in claim 9, wherein the first floating gate transistor has a first channel length, the second floating gate transistor has a second channel length, the third floating gate transistor has a third channel length, and the fourth floating gate transistor has a fourth channel length, wherein the first channel length is larger than the third channel length, and the fourth channel length is larger than the second channel length.

11. The non-volatile memory as claimed in claim 9, wherein the memory cell further comprises:

a first control transistor comprising a first gate, a ninth source/drain terminal and a tenth source/drain terminal, wherein the first gate is connected with a word line, the ninth source/drain terminal is connected with a bit line, and the tenth source/drain terminal is connected with the third terminal of the storage element; and

a second control transistor comprising a second gate, an eleventh source/drain terminal and a twelfth source/drain terminal, wherein the second gate is connected with the word line, the eleventh source/drain terminal is connected with the bit line, and the twelfth source/drain terminal is connected with the fourth terminal of the storage element.

12. The non-volatile memory as claimed in claim 9, wherein the memory cell further comprises:

a first select transistor comprising a third gate, a thirteenth source/drain terminal and a fourteenth source/drain terminal, wherein the third gate is connected with a select line, the thirteenth source/drain terminal is connected with a source line, and the fourteenth source/drain terminal is connected with the first terminal of the storage element; and

a second select transistor comprising a fourth gate, a fifteenth source/drain terminal and a sixteenth source/drain terminal, wherein the fourth gate is connected with the select line, the fifteenth source/drain terminal is connected with the source line, and the sixteenth source/drain terminal is connected with the second terminal of the storage element.

13. The non-volatile memory as claimed in claim 8, wherein the memory cell further comprises q capacitors, and the x-th capacitor is connected between the x-th floating gate and a control line.

14. The non-volatile memory as claimed in claim 8, wherein the memory cell further comprises q capacitors, and the x-th capacitor is connected between the x-th floating gate and an erase line.