SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM CONFIGURED TO PERFORM TRACKING READ ON FIRST MEMORY CELLS FOLLOWED BY SHIFT READ ON SECOND MEMORY CELLS USING READ VOLTAGE CORRECTION VALUE DETERMINED DURING THE TRACKING READ

• US 20190115085A1
• Filed: 11/19/2018
• Published: 04/18/2019
• Est. Priority Date: 08/19/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: KONNO, Hayato, HARADA, Yoshikazu, YANAGIDAIRA, Kosuke, NAKAI, Jun, KAMI, Hiroe, UTSUNOMIYA, Yuko
• Granted Patent: US 10,643,715 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor memory device includes first, second, and third memory cells, and first, second, and third word lines that are respectively connected to gates of the first, second, and third memory cells. A control circuit executes first, second, and third read operations in response to first, second, and third command sets, respectively. The first read operation includes a first read sequence, in which the control circuit reads data by applying first to third voltages to the first word line. In the second read operation, the control circuit reads data by applying a second read voltage that is set based on a result of the first read sequence, to the second word line. In the third read operation, the control circuit reads data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line.

Claims

1. A semiconductor memory device comprising:

a memory cell array including first memory cells and second memory cells;

a first word line connected to gates of the first memory cells;

a second word line connected to gates of the second memory cells; and

a control circuit configured to execute a first read operation in response to a first command set and a second read operation in response to a second command set, wherein

the first command set includes a first command which instructs the control circuit to apply at least first to third voltages to the first word line to read data from the first memory cells and to calculate a read voltage, which is used in a reading operation, based on the data read, and

the second command set includes a second command which instructs the control circuit to read data from the second memory cells by applying the read voltage to the second word line.

2. The device according to claim 1, wherein the control circuit, in response to the first command set, determines a correction value used in calculating the read voltage based on the data read, and stores the correction value.

3. The device according to claim 2, wherein the control circuit, in response to the second command set, calculates the read voltage applied to the second word line based on the stored correction value.

4. The device according to claim 1, wherein

the first command set includes the first command and a read command, which is read by the control circuit after the first command and prior to address information that is also included in the first command set, and

the second command set includes the second command and a read command, which is read by the control circuit after the second command and prior to address information that is also included in the second command set.

5. The device according to claim 1, further comprising:

a third word line connected to gates of third memory cells of the memory cell array, wherein

the control circuit is configured to execute a third read operation in response to a third command set, and

the third command set includes a third command which instructs the control circuit to read data from the third memory cells by applying an uncorrected read voltage to the third word line.

6. The device according to claim 5, further comprising:

a fourth word line connected to gates of fourth memory cells of the memory cell array; and

a fifth word line connected to gates of fifth memory cells of the memory cell array, wherein

the control circuit is configured to execute a fourth read operation in response to a fourth command set, and a fifth read operation in response to a fifth command set,

the fourth command set includes a fourth command which instructs the control circuit to apply at least fourth to sixth voltages to the fourth word line to read data from the fourth memory cells, and

the fifth command set includes a fifth command which instructs the control circuit to read data from the fifth memory cells by applying a read voltage that is calculated based on the data read from the fourth memory cells to the fifth word line.

7. The device according to claim 6, wherein

the first command and the fourth command are each a command to perform tracking read, and the second command and the fifth command are each a command to perform shift read.

8. The device according to claim 7, wherein the third command is a command to perform a normal read.

9. A method of performing a read operation in a semiconductor memory device comprising a memory cell array including first memory cells and second memory cells, a first word line connected to gates of the first memory cells, and a second word line connected to gates of the second memory cells, said method comprising:

in response to a first command set, applying at least first to third voltages to the first word line to read data from the first memory cells and calculating a read voltage, which is used in a reading operation, based on the data read; and

in response to a second command set, applying the read voltage to the second word line to read data from the second memory cells.

10. The method according to claim 9, further comprising:

in response to the first command set, determining a correction value used in calculating the read voltage based on the data read, and storing the correction value.

11. The method according to claim 10, further comprising:

in response to the second command set, calculating the read voltage applied to the second word line based on the stored correction value.

12. The method according to claim 9, wherein

the first command set includes a first command to apply the at least first to third voltages to the first word line to read data from the first memory cells and to calculate the read voltage based on the data read, a read command, and address information, and

the second command set includes a second command to apply the read voltage to the second word line to read data from the second memory cells, a read command, and address information.

13. The method according to claim 9, further comprising:

in response to a third command set, applying an uncorrected read voltage to a third word line connected to gates of third memory cells of the memory cell array to read data from the third memory cells.

14. The method according to claim 13, further comprising:

in response to a fourth command set, applying at least fourth to sixth voltages to a fourth word line connected to gates of fourth memory cells of the memory cell array to read data from the fourth memory cells; and

in response to a fifth command set, applying a read voltage that is calculated based on the data read from the fourth memory cells to a fifth word line connected to gates of fifth memory cells of the memory cell array to read data from the fifth memory cells.

15. The method according to claim 14, wherein

the first command set and the fourth command set each include a command to perform tracking read, and the second command set and the fifth command set each include a command to perform shift read.

16. The method according to claim 15, wherein the third command set includes a command to perform a normal read.