SEMICONDUCTOR DEVICE

• US 20190115295A1
• Filed: 08/07/2018
• Published: 04/18/2019
• Est. Priority Date: 10/13/2017
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: KARIYAZAKI, Shuuichi, TSUCHIYA, Keita, OKAYASU, Yoshitaka, SHIROI, Wataru
• Granted Patent: US 10,643,939 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/06133 with a staggered arrangement, e.g. depopulated array
• CPC Class Codes: H01L 2224/06515 Bonding areas having different functions
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17133 with a staggered arrangement, e.g. depopulated array
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device has a wiring substrate on which a semiconductor chip is mounted. A wiring layer of the wiring substrate has a wiring. This wiring has a main wiring unit extending in a direction “X” and a plurality of sub-wiring units extending in a direction “Y”, in a cross sectional view, and is supplied with a power source potential. The wiring layer has a wiring. This wiring has a main wiring unit extending in the direction “X” and a plurality of sub-wiring units extending in the direction “Y”, in a cross sectional view, and is supplied with a reference potential. The sub-wiring units and the sub-wiring units have end units and end units on a side opposed to the end units, and are alternately arranged along the direction “X” between the main wiring units. To the end units, via wirings are coupled.

Claims

1. A semiconductor device comprising:

a semiconductor chip which has a first surface, a first back surface on a side opposed to the first surface, and a plurality of electrodes arranged on the first surface; and

a wiring substrate which has a first main surface on which the semiconductor chip is mounted, a second main surface on a side opposed to the first main surface, a first wiring layer which is formed between the first main surface and the second main surface, and a second wiring layer which is formed between the first wiring layer and the second main surface and adjacent to the first wiring layer in a cross sectional view in a direction crossing the first main surface,

wherein the first wiring layer has

a first wiring having a first main wiring unit extending in a first direction in a cross sectional view and a plurality of first sub-wiring units, extending in a second direction crossing the first direction and crossing the first main wiring unit, and the first wiring being supplied with a first potential,

a second wiring having a second main wiring unit extending in the first direction in the cross sectional view and a plurality of second sub-wiring units, extending in the second direction and crossing the second main wiring unit, and the second wiring being supplied with a second potential different from the first potential,

wherein the first sub-wiring units of the first wiring and the second sub-wiring units of the second wiring

have a first end unit and a second end unit on a side opposed to the first end unit through the first main wiring unit or the second main wiring unit in the second direction, and

are alternately arranged along the first direction, between the first main wiring unit and the second main wiring unit,

wherein the second wiring has

a first conductor pattern which overlaps with the second main wiring unit of the second wiring and the first end unit of the first sub-wiring units of the first wiring, and extends in the first direction, and

a second conductor pattern which overlaps with the first main wiring unit of the first wiring and the second end unit of the second sub-wiring units of the second wiring,

wherein the first end unit of the first sub-wiring units is electrically coupled with the first conductor pattern through a plurality of first vias, and

wherein the second unit of the second sub-wiring units is electrically coupled with the second conductor pattern through a plurality of vias.

2. The semiconductor device according to claim 1,

wherein the first surface of the semiconductor chip is opposed to the first main surface of the wiring substrate;

wherein the electrodes of the semiconductor chip include

a plurality of first electrodes electrically coupled to the first wiring of the wiring substrate, and

a plurality of second electrodes electrically coupled to the second wiring of the wiring substrate, and

wherein the wiring substrate has

a plurality of first terminals opposed to and electrically coupled with the first electrodes of the semiconductor chip and

a plurality of second terminals opposed to and electrically coupled with the second electrodes of the semiconductor chip.

3. The semiconductor device according to claim 2,

wherein the wiring substrate has a first insulating film covering the first wiring layer and including a plurality of openings,

wherein the first wiring has the first terminals exposed from the first insulating film in the openings included in the first insulating film,

wherein the second wiring has the second terminals exposed from the first insulating film in the openings included in the first insulating film,

wherein the first electrodes of the semiconductor chip and the first terminals are coupled through first bump electrodes, and

wherein the second electrodes of the semiconductor chip and the second terminals are coupled through a second bump electrode.

4. The semiconductor device according to claim 3,

wherein the first terminals include a plurality of third terminals formed in the first end unit and the second end unit of the first sub-wiring units, and

wherein the second terminals include a plurality of fourth terminals formed in the third end unit and the second end unit of the sub-wiring units.

5. The semiconductor device according to claim 4,

wherein the third terminals respectively overlap with the first vias, and

wherein the fourth terminals respectively overlap with the second vias.

6. The semiconductor device according to claim 4,

wherein the first terminals include a fifth terminal formed in the first main wiring unit, and

wherein the second terminals include a sixth terminal formed in the second main wiring unit.

7. The semiconductor device according to claim 6,

wherein the fifth terminal does not overlap with the first vias, and

wherein the sixth terminal does not overlap with the second vias.

8. The semiconductor device according to claim 1,

wherein the second wiring layer has a third conductor pattern overlapping with the second end unit of the first sub-wiring units of the first wiring and extending in the first direction,

wherein the second conductor pattern is provided between the first conductor pattern and the third conductor pattern in a cross sectional view, and

wherein the second end units of the first sub-wiring units are electrically coupled to the third conductor pattern through the first vias.

9. The semiconductor device according to claim 8,

wherein the second wiring layer has the second conductor patterns arranged between the first conductor pattern and the third conductor pattern in the second direction and arranged in one row along the first direction, and

wherein the first conductor pattern and the third conductor pattern are electrically coupled with each other through a connecting unit formed between the second conductor patterns.

10. The semiconductor device according to claim 8,

wherein the second wiring layer has a fourth conductor pattern overlapping with the first end units of the second sub-wiring units of the second wiring,

wherein the first conductor pattern is formed between the second conductor pattern and the fourth conductor pattern in a cross sectional view, and

wherein the first end units of the second sub-wiring units are electrically coupled with the fourth conductor pattern through the second vias.

11. The semiconductor device according to claim 10,

wherein the second wiring layer has the second conductor patterns which are arranged between the first conductor pattern and the third conductor pattern in the second direction, and are arranged in one row along the first direction, and

wherein the second conductor patterns are electrically coupled with each other through the second wiring of the first wiring layer.

12. The semiconductor device according to claim 1,

wherein the wiring substrate has a third wiring layer which is formed between the second wiring layer and the second main surface, and is adjacent to the second wiring layer in a cross sectional view in a direction crossing the first main surface,

wherein the third wiring layer has

a third conductor pattern, overlapping with the first conductor pattern, electrically coupled with the first conductor pattern through a plurality of third vias, and extending in the first direction, and

a fourth conductor pattern, overlapping with the second conductor pattern, electrically coupled with the second conductor pattern through a plurality of fourth vias, and extending in the first direction.

13. The semiconductor device according to claim 12,

wherein the wiring substrate has

a fourth wiring layer formed between the third wiring layer and the second main surface, and

a plurality of through hole wirings for electrically coupling the third wiring layer and the fourth wiring layer, and

wherein the through hole wirings include a plurality of first through hole wirings coupled to the third conductor pattern in the third wiring layer and a plurality of second through hole wirings coupled to the fourth conductor pattern in the third wiring layer.

14. The semiconductor device according to claim 13,

wherein an arrangement pitch of the electrodes of the semiconductor chip is smaller than an arrangement pitch of the through hole wirings of the wiring substrate.

15. The semiconductor device according to claim 1,

wherein the first wiring layer of the wiring substrate has a plurality of first wirings and a plurality of second wirings,

wherein the first wirings and the second wirings are alternately arranged along the second direction, in a cross sectional view.

16. The semiconductor device according to claim 1,

wherein the first wiring layer has a third wiring having a third main wiring unit extending in the first direction in a cross sectional view and a plurality of third sub-wiring units extending in the second direction and crossing the third main wiring unit, and the third wiring being supplied with the second potential,

wherein the first wiring is arranged between the second wiring and the third wiring in the second direction,

wherein the third sub-wiring units of the third wiring have the first end unit and the second end unit on a side opposed to the first end unit through the third main wiring unit in the second direction,

wherein the first sub-wiring units and the third sub-wiring units are alternately arranged along the first direction, between the second main wiring unit and the third main wiring unit,

wherein the second wiring layer has a third conductor pattern overlapping with the third main wiring unit of the third wiring and the second end units of the first sub-wiring units of the first wiring,

wherein the second end units of the first sub-wiring units are electrically coupled with the third conductor pattern through the first vias, and

wherein the first end units of the third sub-wiring units are electrically coupled with the second conductor pattern through the second vias.

17. The semiconductor device according to claim 1,

wherein the first wiring layer has a fourth wiring having a fourth main wiring unit extending in the first direction in a cross sectional view and a plurality of fourth sub-wiring units extending in the second direction and crossing the fourth main wiring unit, the fourth wiring being supplied with the first potential, wherein the second wiring is arranged between the first wiring and the fourth wiring in the second direction,

wherein each of the fourth sub-wiring units of the fourth wiring has the first end unit and the second end unit on a side opposed to the first end unit through the fourth main wiring unit in the second direction,

wherein the second sub-wiring units and the fourth sub-wiring units are alternately arranged along the first direction between the second main wiring unit and the fourth main wiring unit,

wherein the second wiring layer has a fourth conductor pattern overlapping with the fourth main wiring unit of the fourth wiring and the second end units of the first sub-wiring units of the first wiring,

wherein the first end units of the second sub-wiring units are electrically coupled with the fourth conductor pattern through the second vias, and

wherein the first end units of the fourth sub-wiring units are electrically coupled with the first conductor pattern through the first vias.

18. The semiconductor device according to claim 1,

wherein the semiconductor chip has a circuit which is driven by a potential difference between the first potential and the second potential, and

wherein the second potential is a ground potential, and the first potential is a power source potential different from the ground potential.