DIGITALLY ASSISTED FEEDBACK LOOP FOR DUTY-CYCLE CORRECTION IN AN INJECTION-LOCKED PLL

• US 20190115925A1
• Filed: 05/15/2018
• Published: 04/18/2019
• Est. Priority Date: 10/12/2017
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Shu, Guanghua, Liu, Frankie Y., Yang, Suwen, Shehadeh, Ziad Saleh, Chang, Eric Y.
• Granted Patent: US 10,461,755 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H03L 7/0998 using phase interpolation
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

We disclose a system, which performs a duty-cycle correction operation for an injection-locked phase-locked loop (PLL). The system first obtains a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle. The system multiplies the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values. The system then accumulates the duty-cycle distortion values to produce a duty-cycle-error amplitude. Next, the system multiplies the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal. Finally, the system uses the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.

Claims

1. A duty-cycle correction circuit for an injection-locked phase-locked loop (PLL), comprising a digital calibration circuit, which performs a duty-cycle correction operation by:

obtaining a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle;

multiplying the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values;

accumulating the duty-cycle distortion values to produce a duty-cycle-error amplitude;

multiplying the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal; and

using the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.

2. The duty-cycle correction circuit of claim 1, wherein the duty-cycle correction circuit obtains the pattern of positive and negative error pulses from a phase detector in the injection-locked PLL.

3. The duty-cycle correction circuit of claim 1, wherein the DCD template specifies alternating positive and negative signs associated with a duty-cycle error of the reference clock signal.

4. The duty-cycle correction circuit of claim 1, further comprising the injection-locked PLL, wherein the injection-locked PLL comprises:

a reference input, which receives the reference clock signal;

a frequency doubler, which doubles the frequency of the reference clock signal to produce a doubled reference clock signal;

a ring oscillator, which generates an output clock signal;

a phase detector, which detects errors comprising deviations between edges of the output clock signal and the doubled reference clock signal;

a frequency-tracking path, which adjusts a frequency of the ring oscillator based on the detected errors;

a phase-tracking path, which adjusts a phase of the ring oscillator based on the detected errors by injecting pulses into the ring oscillator;

a gating mechanism, which periodically suppresses the injected pulses to allow the frequency-tracking path to detect and remediate frequency errors without interference from concurrent phase adjustments; and

the duty-cycle correction circuit, which corrects errors in the doubled reference clock signal caused by duty-cycle errors in the reference clock signal.

5. The duty-cycle correction circuit of claim 4, wherein while correcting the errors in the doubled reference clock signal, the duty-cycle correction circuit uses the duty-cycle correction signal to control a digitally controlled delay line (DCDL), which introduces corrective delays into the doubled reference clock signal.

6. The clock generator of claim 5, wherein the duty-cycle correction signal is applied to the DCDL during a falling edge of the doubled reference clock signal to correct a timing of a subsequent rising edge of the doubled reference clock signal.

7. The duty-cycle correction circuit of claim 6, wherein the phase-tracking path of the injection-locked PLL comprises:

a digital phase accumulator, which accumulates detected errors from the phase detector to produce a phase-accumulator output;

an adder, which adds the phase-accumulator output to the duty-cycle correction signal to produce a composite correction signal for overall phase adjustment; and

the DCDL that inserts a variable delay, which is determined based on the composite correction signal, into the doubled reference clock signal to produce a corrected doubled reference clock signal.

8. The duty-cycle correction circuit of claim 4, wherein the frequency-tracking path of the injection-locked PLL comprises:

a digital accumulator, which accumulates detected errors from the phase detector;

a digital-to-analog converter, which converts an output of the digital accumulator into an analog reference voltage V_REF; and

a low-dropout voltage regulator, which generates the supply voltage for the ring oscillator based on V_REF, wherein the supply voltage of the ring oscillator affects a frequency of the ring oscillator.

9. The duty-cycle correction circuit of claim 4, wherein the phase detector of the injection-locked PLL comprises a bang-bang phase detector.

10. A method of performing a duty-cycle correction operation for an injection-locked phase-locked loop (PLL), comprising:

obtaining a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle;

multiplying the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values;

accumulating the duty-cycle distortion values to produce a duty-cycle-error amplitude;

multiplying the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal; and

using the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.

11. The method of claim 10, wherein the pattern of positive and negative error pulses is obtained from a phase detector in the injection-locked PLL.

12. The method of claim 10, wherein the DCD template specifies alternating positive and negative signs associated with a duty-cycle error of the reference clock signal.

13. The method of claim 10, wherein the injection-locked PLL comprises:

a reference input, which receives the reference clock signal;

a frequency doubler, which doubles a frequency of the reference clock signal to produce a doubled reference clock signal;

a ring oscillator, which generates an output clock signal;

a phase detector, which detects errors comprising deviations between edges of the output clock signal and the doubled reference clock signal;

a frequency-tracking path, which adjusts a frequency of the ring oscillator based on the detected errors;

a phase-tracking path, which adjusts a phase of the ring oscillator based on the detected errors by injecting pulses into the ring oscillator;

a gating mechanism, which periodically suppresses the injected pulses to allow the frequency-tracking path to detect and remediate frequency errors without interference from concurrent phase adjustments; and

a duty-cycle correction circuit, which corrects errors in the doubled reference clock signal caused by duty-cycle errors in the reference clock signal.

14. The method of claim 13, wherein while correcting the errors in the doubled reference clock signal, the duty-cycle correction circuit uses the duty-cycle correction signal to control a digitally controlled delay line (DCDL), which introduces corrective delays into the doubled reference clock signal.

15. The method of claim 14, wherein the duty-cycle correction signal is applied to the DCDL during a falling edge of the doubled reference clock signal to correct a timing of a subsequent rising edge of the doubled reference clock signal.

16. The method of claim 15, wherein the phase-tracking path of the injection-locked PLL comprises:

a digital phase accumulator, which accumulates detected errors from the phase detector to produce a phase-accumulator output;

an adder, which adds the phase-accumulator output to the duty-cycle correction signal to produce a composite correction signal; and

the DCDL that inserts a variable delay, which is determined based on the composite correction signal, into the doubled reference clock signal to produce a corrected doubled reference clock signal.

17. The method of claim 13, wherein the frequency-tracking path of the injection-locked PLL comprises:

a digital accumulator, which accumulates detected errors from the phase detector;

a digital-to-analog converter, which converts an output of the digital accumulator into an analog reference voltage V_REF; and

a low-dropout voltage regulator, which generates the supply voltage for the ring oscillator based on V_REF, wherein the supply voltage of the ring oscillator affects a frequency of the ring oscillator.

18. The method of claim 13, wherein the phase detector of the injection-locked PLL comprises a bang-bang phase detector.

19. A computer system, comprising:

at least one processor and at least one associated memory; and

a clock generator that provides a clock signal for the at least one processor, wherein the clock generator is implemented using an injection-locked phase-locked loop (PLL), and includes a duty-cycle correction;

wherein the duty-cycle correction comprises a digital circuit, which performs a duty-cycle correction operation by;

obtaining a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle,

multiplying the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values;

accumulating the duty-cycle distortion values to produce a duty-cycle-error amplitude,

multiplying the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal, and

using the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.

20. The computer system of claim 19, wherein while compensating for timing errors in the injection-locked PLL, the duty-cycle correction circuit uses the duty-cycle correction signal to control a digitally controlled delay line (DCDL), which introduces corrective delays into a reference clock signal for the injection-locked PLL.