ARRAY SUBSTRATE AND DISPLAY PANEL

• US 20190121211A1
• Filed: 10/24/2018
• Published: 04/25/2019
• Est. Priority Date: 10/25/2017
• Status: Active Grant

• Current Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Original Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Inventors: LUO, Xiaodong, SHEN, Poping, ZHOU, Xiufeng
• Granted Patent: US 10,852,604 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/1333 Constructional arrangements; Manufacturing methodsG02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 2201/56 Substrates having a particular shape, e.g. non-rectangular
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/1315 comprising structures specially adapted for lowering the resistance

Abstract

An array substrate includes: a display region, a non-display region surrounding the display region, at least one notch in the non-display region, and multiple gate lines. The gate lines include regular gate lines and irregular gate lines. The regular gate line is located in the display region and extends in a first direction. The irregular gate line includes a regular section located in the display region and extends in the first direction and an irregular section located in the non-display region around the notch. The regular section and the irregular section of the same irregular gate line are electrically connected. The irregular section includes a first sub-section and/or a second sub-section. The first sub-section and the second sub-section of the same irregular section are electrically connected to each other. A resistivity of the first sub-section is greater than a resistivity of the second sub-section.

Claims

1. An array substrate, comprising:

a display region;

a non-display region surrounding the display region;

at least one notch in the non-display region; and

a plurality of gate lines,

wherein the plurality of gate lines comprises regular gate lines and irregular gate lines, wherein each of the regular gate lines is located in the display region and extends in a first direction;

wherein each of the irregular gate lines comprises a regular section located in the display region and extends in the first direction and an irregular section located in the non-display region around the notch, wherein the regular section and the irregular section of the same irregular gate line are electrically connected to each other; and

wherein the irregular section comprises at least one of a first sub-section and a second sub-section, wherein the first sub-section and the second sub-section of the same irregular section are electrically connected to each other, and a resistivity of the first sub-section is greater than a resistivity of the second sub-section.

2. The array substrate according to claim 1, further comprising a substrate layer, a first metal layer and a second metal layer,

wherein the first metal layer is located at a surface of the substrate layer, the second metal layer is located over a surface of the first metal layer facing away from the substrate layer;

and

wherein the regular gate lines, the regular sections and the first sub-sections, are located in the first metal layer, and the second sub-sections are located in the second metal layer.

3. The array substrate according to claim 2, wherein an orthographic projection of a part of the second sub-section on the substrate layer partially overlaps an orthographic projection of a part of the first sub-section, on the substrate layer.

4. The array substrate according to claim 1, wherein

the irregular gate lines comprise first irregular gate lines and second irregular gate lines, a length of an irregular section of the first irregular gate line is greater than a length of an irregular section of the second irregular gate line;

the irregular section comprises a first sub-section and a second sub-section, and a length of the second sub-section of the first irregular gate line is greater than a length of the second sub-section of the second irregular gate line.

5. The array substrate according to claim 4, comprising a first edge, wherein

the first edge comprises a regular edge extended in a first direction and an irregular edge recessed into the display region, and the irregular edge forms the notch;

and

the irregular section comprises the first sub-section and the second sub-section;

in a second direction from the first edge to the display region, lengths of the first sub-sections of the irregular gate lines are gradually increased, and lengths of the second sub-sections of the irregular gate lines are gradually decreased, wherein the second direction is perpendicular to the first direction.

6. The array substrate according to claim 5, wherein only one end of the irregular edge is connected to the regular edge.

7. The array substrate according to claim 5, wherein two ends of the irregular edge are connected to the regular edge;

and

the regular section comprises a first sub-regular section and a second sub-regular section;

in the first direction, the first sub-regular section and the second sub-regular section are respectively located on both sides of the notch in the first direction, and two ends of the irregular section are electrically connected to the first sub-regular section and the second sub-regular section of the same irregular gate line.

8. The array substrate according to claim 4,

wherein a through hole is arranged at a geometric center portion of the array substrate to form the notch;

wherein the display region of the array substrate comprises a second edge and a third edge in a second direction which are located at both sides of the notch, and the second direction is perpendicular to the first direction;

wherein the regular section comprises a first sub-regular section and a second sub-regular section;

in the first direction, the first sub-regular section and the second sub-regular section are respectively located at both sides of the notch in the first direction, and two ends of the irregular section are electrically connected to the first sub-regular section and the second sub-regular section of the same irregular gate line;

wherein the irregular section is located at least one of a position between the second edge and the notch and a position between the third edge and the notch;

wherein the irregular section comprises a first sub-section and a second sub-section;

for the irregular section located between the second edge and the notch, in a second direction from the second edge to the notch, lengths of the first sub-sections of the irregular sections are gradually decreased, and lengths of the second sub-sections in the irregular sections are gradually increased; and

for the irregular section located between the third edge and the notch, in the second direction from the third edge to the notch, lengths of the first sub-sections of the irregular sections are gradually decreased, and lengths of the second sub-sections of the irregular sections are gradually increased.

9. The array substrate according to claim 1, wherein

in the first direction, the non-display region comprises a first non-display region and a second non-display region located at two opposite sides of the display region;

the first non-display region is provided with a first shift register group, the second non-display region is provided with a second shift register group;

the first shift register group comprises a plurality of cascaded first shift registers, and the second shift register group comprises a plurality of cascaded second shift registers; and

in the second direction, the gate lines are alternately electrically connected to the first shift registers and the second shift registers, wherein the second direction is perpendicular to the first direction.

10. The array substrate according to claim 1, wherein

in the first direction, the non-display region comprises a first non-display region and a second non-display region located at two opposite sides of the display region;

the first non-display region is provided with a first shift register group, the second non-display region is provided with a second shift register group;

the first shift register group comprises a plurality of cascaded first shift registers, and the second shift register group comprises a plurality of cascaded second shift registers; and

two ends of each of the gate lines are electrically connected to the first shift register and the second shift register respectively.

11. The array substrate according to claim 1, wherein

in the first direction, the non-display region comprises a first non-display region and a second non-display region located at two opposite sides of the display region;

and

only the first non-display region is provided with a first shift register group, the first shift register group comprises a plurality of cascaded first shift registers, and the gate lines are electrically connected to the first shift registers;

or

only the second non-display region is provided with a second shift register group, the second shift register group comprises a plurality of cascaded second shift registers, and the gate lines are electrically connected to the second shift registers.

12. The array substrate according to claim 1, wherein the notch is rectangular, a trapezoidal, or triangular.

13. A display panel, comprising an array substrate, wherein the array substrate comprises:

a display region;

a non-display region surrounding the display region;

at least one notch in the non-display region; and

a plurality of gate lines,

wherein the plurality of gate lines comprises regular gate lines and irregular gate lines, wherein each of the regular gate lines is located in the display region and extends in a first direction;

wherein each of the irregular gate lines comprises a regular section located in the display region and extends in the first direction and an irregular section located in the non-display region around the notch, wherein the regular section and the irregular section of the same irregular gate line are electrically connected to each other; and

wherein the irregular section comprises at least one of a first sub-section and a second sub-section, wherein the first sub-section and the second sub-section of the same irregular section are electrically connected to each other, and a resistivity of the first sub-section is greater than a resistivity of the second sub-section.