MEMORY-MAPPED INTERFACE FOR MESSAGE PASSING COMPUTING SYSTEMS

• US 20190121734A1
• Filed: 10/20/2017
• Published: 04/25/2019
• Est. Priority Date: 10/20/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Akopyan, Filipp A., Arthur, John V., Cassidy, Andrew S., DeBole, Michael V., Merolla, Paul A., Modha, Dharmendra S., Sawada, Jun
• Granted Patent: US 10,452,540 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/063 for I/O modules, e.g. memory mapped I/O I/O protocol G06F13/42
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/10 Interfaces, programming languages or software development kits, e.g. for simulating neural networks
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

Memory-mapped interfaces for message passing computing systems are provided. According to various embodiments, a write request is received. The write request comprises write data and a write address. The write address is a memory address within a memory map. The write address is translated into a neural network address. The neural network address identifies at least one input location of a destination neural network. The write data is sent via a network according to the neural network address to the at least one input location of the destination neural network. A message is received via the network from a source neural network. The message comprises data and at least one address. A location in a buffer is determined based on the at least one address. The data is stored at the location in the buffer. The buffer is accessible via the memory map.

Claims

1. A system comprising:

a neural network processor system, comprising at least one neural network processing core interconnected by a network;

an interface operatively connected to the network, the interface comprising a memory map, the memory map comprising a first region corresponding to inputs to the neural network processor system and a second region corresponding to outputs from the neural network processor system.

2. The system of claim 1, wherein:

the interface is adapted to receive a write request comprising write data and a write address, the write address corresponding to a location within the first region of the memory map;

the interface is adapted to send the write data via the network to at least one input location of a destination neural network processing core;

the interface is adapted to receive a read request comprising a read address, the read address corresponding to a location within the second region of the memory map;

the interface is adapted to return read data to an originator of the read request, the read data comprising an output of a source neural network processing core.

3. The system of claim 2, wherein the interface comprises an address translator, the address translator being adapted to:

translate the write address into a target address, the target address identifying the at least one input location of the destination neural network processing core.

4. The system of claim 2, wherein the interface comprises an address translator and wherein:

the interface is adapted to receive a message via the network from the source neural network processing core, the message comprising data and at least one address;

the address translator is adapted to determine an address within the second region of the memory map based on the at least one address;

the interface is adapted to provide the data in response to a read request comprising the address within the second region.

5. The system of claim 2, further comprising:

a bus operatively coupled to the interface, wherein;

the interface is adapted to receive the write request via the bus;

the interface is adapted to receive the read request via the bus.

6. The system of claim 2, wherein the at least one neural network processing core comprises a neurosynaptic core and the network comprises an inter-core network, the neurosynaptic core having a plurality of input axons and output neurons.

7. The system of claim 6, wherein the destination neural network processing core is a neurosynaptic core and wherein the write address corresponds to one or more input axons of the neurosynaptic core, and wherein the write data comprises a plurality of axon inputs to the neurosynaptic core.

8. The system of claim 6, wherein the source neural network processing core is a neurosynaptic core and wherein the read address corresponds to one or more output neurons of the neurosynaptic core, and wherein the read data comprises a plurality of neuron outputs of the neurosynaptic core.

9. The system of claim 3, wherein the translating comprises applying a predetermined function.

10. The system of claim 3, wherein the translating comprises accessing a lookup table.

11. The system of claim 2, wherein the interface comprises a buffer and wherein:

the interface is adapted to receive a message via the network from the source neural network processing core, the message comprising message data and at least one address;

the interface is adapted to store the message data in the buffer at a location, and wherein the at least one address corresponds to the location in the buffer.

12. The system of claim 1, further comprising:

a sensor operatively connected to the interface, the sensor being adapted to transmit sensor outputs to the neural network processor system via the interface.

13. The system of claim 1, further comprising:

an actuator operatively connected to the interface, the actuator being adapted to receive inputs from the neural network processor system via the interface.

14. The system of claim 1, further comprising:

a computing node operatively coupled to the interface, the computing node being adapted to access the interface via DMA.

15. The system of claim 1, further comprising:

a computing node operatively coupled to the interface, the computing node being adapted to access the interface via a bus.

16. The system of claim 15, wherein the computing node, the interface, and the neural network processor system are located on a single chip.

17. A method comprising:

receiving a write request comprising write data and a write address, the write address being a memory address within a memory map;

translating the write address into a neural network address, the neural network address identifying at least one destination neural network input location;

sending the write data via a network according to the neural network address to the at least destination neural network input location.

18. The method of claim 17, wherein the write request is received via a bus.

19. The method of claim 17, wherein the network is an inter-core network.

20. The method of claim 17, wherein the destination neural network comprises a neurosynaptic core.

21. The method of claim 17, wherein the translating comprises applying a predetermined function.

22. The method of claim 17, wherein the translating comprises accessing a lookup table.

23. The method of claim 17, wherein the write data comprises a plurality of axon inputs.

24. The method of claim 17, further comprising:

receiving the write data at an input buffer of the destination neural network.

25. A method comprising:

receiving a message via a network from a source neural network, the message comprising data and at least one address;

storing the data at a location in a buffer, the buffer being accessible via a memory map.

26. The method of claim 25, further comprising:

receiving a read request comprising a read address, the read address being a memory address within the memory map and corresponding to the location in the buffer;

returning the data to an originator of the read request.

27. The method of claim 26, wherein the read request is received via a bus.

28. The method of claim 25, wherein the source neural network is a neurosynaptic core.

29. The method of claim 25, wherein the data comprises a plurality of neuron outputs.

30. A computer program product for interfacing a memory mapped system with a message passing system, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:

receiving a write request comprising write data and a write address, the write address being a memory address within a memory map;

translating the write address into a neural network address, the neural network address identifying at least one input location of a destination neural network;

sending the write data via a network according to the neural network address to the at least one input location of the destination neural network;

receiving a message via the network from a source neural network, the message comprising data and at least one address;

determining a location in a buffer based on the at least one address;

storing the data at the location in the buffer, the buffer being accessible via the memory map.