MEMORY DEVICE AND PROGRAMMING OPERATION METHOD THEREOF WITH DIFFERENT BIT LINE VOLTAGES

• US 20190122735A1
• Filed: 10/25/2017
• Published: 04/25/2019
• Est. Priority Date: 10/25/2017
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lee, Ya-Jui, Chen, Kuan-Fu
• Granted Patent: US 10,460,808 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/32 Timing circuits

Abstract

Provided is an operation method for a memory device. The memory device includes a memory array having a plurality of word lines and a plurality of bit lines. The operation method for the memory device includes: applying a program voltage to at least one selected word line of the word lines; and during a high level of the program voltage, based on respective locations of a plurality of selected bit line, which are to be written into data 0, on the word lines, applying different plurality of bit line voltages to the selected bit line which are to be written into data 0.

Claims

1. An operation method for a memory device having a memory array including a plurality of memory cells, a plurality of word lines and a plurality of bit lines, the operation method for the memory device including:

applying a program voltage to at least a selected word line of the word lines; and

during a high level period of the program voltage, based on respective locations of a plurality of selected bit lines of the bit lines on the word lines, applying a plurality of different bit line voltages to the selected bit lines, wherein the selected bit lines are coupled to at least one memory cell of the memory cells, which is to be written logic 0;

the plurality of different bit line voltage applied to the selected bit lines have different rising transition timing; and

a plurality of first selected bit lines of the selected bit lines, which are closest to a head of the word lines, are applied by the bit line voltage having a fastest rising transition timing or a highest bit line voltage.

2. The operation method for the memory device according to claim 1, wherein

as for the plurality of first selected bit lines and a plurality of second selected bit lines of the selected bit lines, the plurality of first selected bit lines are closer to the head of the word lines than the plurality of second selected bit lines, and

during the high level period of the program voltage, applying a first bit line voltage and a second bit line voltage to the plurality of first selected bit lines and the plurality of second selected bit lines, respectively, wherein a first high level of the first bit line voltage is higher than a second high level of the second bit line voltage, and/or the first bit line voltage has a rising transition timing earlier than the second bit line voltage.

3. An operation method for a memory device having a memory array including a plurality of word lines and a plurality of bit lines, the bit lines being grouped into a plurality of bit line groups based on respective locations of the bit lines on the word lines, the operation method for the memory device including:

applying a program voltage to at least a selected word line of the word lines; and

during a high level period of the program voltage, applying a plurality of different bit line voltages to the selected bit line groups, wherein the plurality of different bit line voltage have different rising transition timing; and

a first selected bit line group of the selected bit line groups, which is closest to a head of the word lines, is applied by the bit line voltage having a fastest rising transition timing or a highest bit line voltage.

4. The operation method for the memory device according to claim 3, wherein

among the selected bit line groups, the first selected bit line group is closer to the head of the word lines than a second selected bit line group, and

during the high level period of the program voltage, applying a first bit line voltage and a second bit line voltage to the first selected bit line group and the second selected bit line group, respectively, wherein a first high level of the first bit line voltage is higher than a second high level of the second bit line voltage, and/or the first bit line voltage has a rising transition earlier than the second bit line voltage.

5. The operation method for the memory device according to claim 3, wherein each of the bit line groups includes the same number of the bit lines.

6. The operation method for the memory device according to claim 3, wherein each of the bit line groups includes a different number of the bit lines.

7. The operation method for the memory device according to claim 3, wherein

during the high level period of the program voltage, respective high levels of the bit line voltages applied to the selected bit line groups are equally distributed between a voltage source and a low level.

8. The operation method for the memory device according to claim 3, wherein

during the high level period of the program voltage, respective high levels of the bit line voltages applied to the selected bit line groups are unequally distributed between a voltage source and a low level.

9. A memory device, including:

a memory array including a plurality of memory cells, a plurality of word lines and a plurality of bit lines;

a control circuit coupled to the memory array; and

an operation voltage generation circuit, coupled to the memory array and the control circuit, for generating a program voltage to at least a selected word line of the word lines of the memory array;

wherein under control of the control circuit, during a high level period of the program voltage, based on respective locations of a plurality of selected bit lines of the bit lines on the word lines, the operation voltage generation circuit applies a plurality of different bit line voltages to the selected bit lines, wherein the selected bit lines are coupled to at least one memory cell of the memory cells, which is to be written logic 0;

the plurality of different bit line voltage have different rising transition timing; and

a plurality of first selected bit lines of the selected bit lines, which are closest to a head of the word lines, are applied by the bit line voltage having a fastest rising transition timing or a highest bit line voltage.

10. The memory device according to claim 9, wherein

as for the plurality of first selected bit lines and a plurality of second selected bit lines of the selected bit lines, the plurality of first selected bit lines are closer to the head of the word lines than the plurality of second selected bit lines, and

during the high level period of the program voltage, the operation voltage generation circuit applies a first bit line voltage and a second bit line voltage to the plurality of first selected bit lines and the plurality of second selected bit lines, respectively, wherein a first high level of the first bit line voltage is higher than a second high level of the second bit line voltage, and/or the first bit line voltage has a rising transition earlier than the second bit line voltage.