BARRIER MODULATED CELL STRUCTURES WITH INTRINSIC VERTICAL BIT LINE ARCHITECTURE

• US 20190123276A1
• Filed: 10/25/2017
• Published: 04/25/2019
• Est. Priority Date: 10/25/2017
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Ratnam, Perumal, Kumar, Tanmay, Petti, Christopher
• Granted Patent: US 10,388,870 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0009 RRAM elements whose operation depends upon chemical change
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
• CPC Class Codes: H10B 63/82 the switching components having a common active material layer
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/021 Formation of the switching material, e.g. layer deposition
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8416 adapted for supplying ionic species
• CPC Class Codes: H10N 70/882 : Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

Systems and methods for reducing leakage currents through unselected memory cells of a memory array including setting an adjustable resistance bit line structure connected to the unselected memory cells into a high resistance state or a non-conducting state during a memory operation are described. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is electrically isolated from the intrinsic polysilicon portion (e.g., via an oxide layer between the intrinsic polysilicon portion and the select gate portion). The memory cells may comprise a first conductive metal oxide (e.g., titanium oxide) that abuts a second conductive metal oxide (e.g., aluminum oxide) that abuts a layer of amorphous silicon.

Claims

1. A method for fabricating a non-volatile memory, comprising:

forming an alternating stack of sacrificial layers and dielectric layers;

etching a memory hole extending through the alternating stack of sacrificial layers and dielectric layers;

depositing a first set of memory element layers within the memory hole;

depositing a material corresponding with an adjustable resistance bit line within the memory hole;

depositing a first dielectric layer within the memory hole;

depositing a conducting material corresponding with a select gate within the memory hole;

etching a second hole extending through the alternating stack of sacrificial layers and dielectric layers;

removing at least a portion of the sacrificial layers;

depositing a second set of memory element layers within the second hole, the second set of memory element layers directly contacts the first set of memory element layers;

depositing a second conducting material corresponding with a word line layer within the second hole;

removing at least a portion of the second set of memory element layers; and

removing at least a portion of the second conducting material.

2. The method of claim 1, wherein:

the first set of memory element layers comprises a layer of titanium oxide;

the second set of memory element layers comprises a layer of one of amorphous silicon, amorphous germanium, or amorphous silicon germanium; and

a portion of the first set of memory element layers and a portion of the second set of memory element layers form a memory cell between the word line layer and the adjustable resistance bit line.

3. The method of claim 1, wherein:

a portion of the first set of memory element layers and a portion of the second set of memory element layers arranged between a first word line associated with the word line layer and the adjustable resistance bit line comprises a memory cell between the first word line and the adjustable resistance bit line.

4. The method of claim 1, wherein:

the sacrificial layers comprise silicon nitride.

5. The method of claim 1, wherein:

the material corresponding with the adjustable resistance bit line comprises one of undoped polysilicon, undoped silicon germanium, or undoped indium gallium arsenide.

6. The method of claim 1, wherein:

the second set of memory element layers comprises a first layer of one of aluminum oxide or zirconium oxide and a second layer of one of amorphous silicon, amorphous germanium, or amorphous silicon germanium.

7. The method of claim 1, wherein:

the non-volatile memory configured to adjust a resistance of the adjustable resistance bit line based on a first voltage applied to the select gate.

8. The method of claim 1, wherein:

the non-volatile memory configured to set the adjustable resistance bit line into a non-conducting state based on a first voltage applied to the select gate.

9. The method of claim 1, wherein:

the adjustable resistance bit line is substantially orthogonal to a substrate.

10. The method of claim 1, wherein:

the removing the at least the portion of the second conducting material electrically isolates at least two word lines within the word line layer.

11-20. -20. (cancelled)