COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS
1. A solid-state device comprising:
- a. first and second complementary field effect transistors, each comprising a gate, a source and a drain, wherein the source and drain of the first transistor define a first channel and the source and drain of the second transistor define a second channel;
b. a first diffusion (first iPort) that divides the first channel into a first source channel segment between the source and the first iPort and a first drain channel segment between the first iPort and the drain, and a second diffusion (second iPort) that divides the second channel into a second source channel segment between the source and the second iPort and a second drain channel segment between the second iPort and the drain;
c. the gate of the first transistor is coupled to the first source channel segment and the first drain channel segment,d. the gate of the second transistor is coupled to the second source channel segment and the second drain channel segment.
The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.
|Super-saturation current field effect transistor and trans-impedance MOS device|
Patent #US 10,446,547 B2
Current AssigneeCircuit Seed LLC
Sponsoring EntityCircuit Seed LLC
|Multi-stage and feed forward compensated complementary current field effect transistor amplifiers|
Patent #US 10,491,177 B2
Current AssigneeCircuit Seed LLC
Sponsoring EntityCircuit Seed LLC
|Reference generator and current source transistor based on complementary current field-effect transistor devices|
Patent #US 10,514,716 B2
Current AssigneeCircuit Seed LLC
Sponsoring EntityCircuit Seed LLC
- 1. A solid-state device comprising:
a. first and second complementary field effect transistors, each comprising a gate, a source and a drain, wherein the source and drain of the first transistor define a first channel and the source and drain of the second transistor define a second channel; b. a first diffusion (first iPort) that divides the first channel into a first source channel segment between the source and the first iPort and a first drain channel segment between the first iPort and the drain, and a second diffusion (second iPort) that divides the second channel into a second source channel segment between the source and the second iPort and a second drain channel segment between the second iPort and the drain; c. the gate of the first transistor is coupled to the first source channel segment and the first drain channel segment, d. the gate of the second transistor is coupled to the second source channel segment and the second drain channel segment.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
- 12. A solid-state device comprising:
e. first and second complementary field effect transistors, each comprising a source gate terminal, a drain gate terminal, a source and a drain, wherein the source and drain of the first transistor define a first channel and the source and drain of the second transistor define a second channel; f. a first diffusion (first iPort) that divides the first channel into a first source channel segment between the source and the first iPort and a first drain channel segment between the first iPort and the drain, and a second diffusion (second iPort) that divides the second channel into a second source channel segment between the source and the second iPort and a second drain channel segment between the second iPort and the drain; g. the source gate terminal of the first transistor being coupled to the first source channel segment;
the drain gate terminal of the first transistor being coupled to the first drain channel segment;
the source gate terminal of the second transistor being coupled to the second source channel segment; and
the drain gate terminal of the second transistor being coupled to the second drain channel segment.
- View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
The present application is a divisional of U.S. patent application Ser. No. 15/748,305, filed Jan. 29, 2018, entitled “COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS”, which is a 35 U.S.C. § 371 National Stage Entry of, and claims priority to, International Application No. PCT/US2015/042696, filed Jul. 29, 2015, entitled “COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS,” the entire disclosure of which is incorporated herein by reference.
The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits.
The new millennium brings with it a demand for connectivity that is expanding at an extremely rapid pace. By the end of year 2015, the number of global network connections will exceed two times the world population and it is estimated that in 2020 more than 30 billion devices will be wirelessly connected to the cloud forming the Internet of Things (or “IoT”). Enabling this new era are the revolutionary developments in mobile computing and wireless communication that have arisen over the last two decades. Following Moore'"'"'s Law, development of highly-integrated and cost-effective silicon complementary metal oxide semiconductor (CMOS) devices allowed incorporation of digital and analog system elements, such as bulky Analog-to-Digital converters or transceivers, into a more cost effective single chip solution.
In the last few years, however, while digital circuits have largely followed the predicted path and benefited from the scaling of CMOS technology into ultra-deep submicron (sub-μm), analog circuits have not been enabled to follow the same trend, and may never be enabled without a paradigm shift in analog design. Analog and radio frequency (or “RF”) designers still struggle to discover how to make high-performance integrated circuits (or “ICs”) for ultra-deep sub-μm feature sizes without losing the benefits of shrinking size; including reduced power, compact footprint, and higher operational frequencies. Truly a paradigm shift is needed to break through the established science of analog design to meet the system on chip (SoC) demands of the new millennium.
The core building block of analog circuits is the amplifier. Discrete component amplifiers are free to use resistors, capacitors, inductors, transformers, and non-linear elements as well as various types of transistors. Unwanted parasitics between various components are normally negligible. However, in order to build amplifiers within an integrated circuit, the normal analog circuit components are not readily available, and often take special IC process extensions to obtain these circuit elements if at all. The parasitics on integrated circuit amplifiers are severe due to their close proximity and being coupled together through the silicon wafer they are integrated into. Moore'"'"'s law IC process advancements are focused on digital, microprocessor, and memory process development. It takes a generation (˜18 months) or two to extend the IC process to incorporate analog components, thus analog functionality is generally not included on the latest process single chip systems. These “mixed-mode” IC processes are less available, vender dependent, and more expensive as well as being highly subject to parametric variation. It takes substantial engineering to include sparse analog functionality on any IC which becomes specific to its IC vender and process node. Because analog circuitry is carefully and specifically designed or arranged for each process node, such analog circuitry is highly non-portable. Eliminating this limitation, analog circuit design engineers are becoming scarce and are slowly retiring without adequate replacements.
Operational Amplifiers (or OpAmps) are the fundamental IC analog gain block necessary to process analog information. OpAmps make use of a very highly matched pair of transistors to form a differential pair of transistors at the voltage inputs. Matching is a parameter that is readily available on an integrated circuit, but to approach the required level of matching, many considerations are used: like centroid layout, multiple large devices, well isolation, and physical layout techniques among many other considerations. Large area matched sets of transistors are also used for current mirrors and load devices. OpAmps require current sources for biasing. OpAmps further require resistor and capacitor (or RC) compensation poles to prevent oscillation. Resistors are essential for the “R” and the value of the RC time constant is relatively precise. Too big value for a resistor would make the amplifier too slow and too small results in oscillation. Constant “bias” currents add to the power consumed. In general, these bias currents want to be larger than the peak currents required during full signal operation.
As IC processes are shrunk, the threshold voltages remain somewhat constant. This is because the metal-oxide-semiconductor (or MOS) threshold cutoff curve does not change with shrinking of the IC processes and the total chip OFF leakage current must be kept small enough to not impact the full-chip power supply leakage. The threshold and saturation voltage tends to take up the entire power supply voltage, not leaving enough room for analog voltage swings. To accommodate this lack of signal swing voltage, OpAmps were given multiple sets of current mirrors, further complicating their design, while consuming more power and using additional physical layout area. This patent introduces amplifier designs that operate even better as power supply voltages are shrunk far below 1 volt.
Prior art CMOS integrated circuit amplifiers are based on several analog or mixed-mode IC process extensions which are not available on all-digital IC processes. Primarily matched pairs of transistors are used as a differential inputs and current mirrors. These analog FET transistors must be long, as depicted in
The conventional MOS amplifier gain formation is an input voltage driving a trans-conductance (gm) which converts the input voltage into an output current. This output current then drives an output load which is normally the output of a current source for the purpose of establishing a high load resistance. This high resistance load converts the output current back into an output voltage. The resulting amplifier voltage gain is gm*Rload. The equivalent output load resistance is actually the parallel combination of the load current source transistor and the amplifier output transistors. In order to keep this equivalent load resistance high, and the voltage gain high, these parallel transistors must be very long, but to drive enough current, these transistors must be very wide to carry sufficient current also, thus very large transistors are necessary. It also might be noted that the load resistance the amplifier output drives is also an additional parallel resistance that reduces the voltage gain. It should also be noted that a load capacitance interacts with the amplifiers output resistance, modifying the AC performance characteristics. What is actually needed is exactly the opposite of the present analog amplifier operating principles of very small voltage-input to high-impedance current-output (gm); which the present invention is about: very small current-input to low-impedance voltage-output (rm).
The baseline comparisons are (all made in a 180 nm IC process) in the form of performance plots as in: a Bode Gain-Phase plot
Normally MOS amplifiers operate within a square-law form due to the strong-inversion MOS transistor square-law characteristics; these are not very well defined or predictably stable to the degree that analog circuits need. Exponential-law operation, like bipolar transistors operation is higher gain, stable, and well defined. At very weak operating conditions, MOS transistors convert to exponential operation, but they are too slow to be of very much use. Furthermore, the “moderate-inversion” transition between these two operating mode provide non-linarites that lower the quality of analog MOS circuits. At the threshold voltage, where MOS transistors operate around, is where 50% of the current is square-law and the other 50% is exponential. This is the definition of threshold voltage in the latest MOS simulation equations. Full exponential MOS operation at high speed would provide higher gain that is predictable, stable, and well defined. This patent is about fast amplifiers that operate in the exponential mode but not in weak-inversion; instead a super-saturated mode is introduced.
To understand the prior art, let'"'"'s begin with a discussion of weak vs. strong-inversion (Enz, Christian C. et al., “Charge-based MOS Transistor Modeling—The EKV model for low-power and RF IC Design, John Wiley & Son Ltd., 2006). Referring to
- Weak conduction channel inversion 13e occurs when the Gate 17e on the body/substrate 16e is operated below its threshold voltage Vthreshold 17f in
FIG. 1fwith channel ionization 13e characterized by a thin surface layer;
- Source 14e to Drain 19e voltage 19f is small (typically less than 100 mV);
- For weak-inversion, the gate G 17e is typically operated by gate voltage supply 12e at a low potential (˜300 mV);
- This creates a channel surface conduction layer 13e, of uniform depth from source S 14e to drain D 19e;
- Since there is essentially zero voltage gradient along the channel 13e (˜no electric field), any current between drain D 19e and source S 14e is primarily supported by diffusion;
- Increased gate voltage Vgs 12e at the gate G 17e increases the thickness of the conduction layer 13e below the gate 17e, thus allowing more charge to diffuse along the channel 13e;
- The conductivity of this surface layer is exponentially related to the gate voltage Vgs 12e at the gate G 17e;
- This exponential relationship holds over as many as 6 decades of dynamic analog signal range for the drain channel current;
- The channel appears as a moderately high value resistor for its channel current (many 100+s of K-Ohms);
- The resulting uniform conduction channel depth promotes higher exponential gain but at a severe speed penalty due to low current density; and
- This weak-inversion conduction is reflected in a near zero operating point 13f in
- Weak conduction channel inversion 13e occurs when the Gate 17e on the body/substrate 16e is operated below its threshold voltage Vthreshold 17f in
Strong conduction channel inversion occurs when the gate voltage Vgs 12g at the Gate 17g on the body/substrate 16g is operated above its threshold voltage 17h (referring to
- Strong conduction channel inversion 15g and 15h occurs when the Drain 19g to Source 14g voltage 19h is larger than the threshold Vthreshold 17h in
FIG. 1h(typically in excess of 400 mV);
- The Gate 17g is operated above its threshold voltage Vthreshold 17h in
- In strong-inversion 18g, the Drain 19g voltage is typically operated above the Gate 17g voltage which results in a pinched-off conduction channel 15g near the Drain 19g;
- This pinched-off channel at 15g gives rise to high output impedance at the Drain 19g and can be observed as the thick flat part 18h of the operating characteristic plot
- As the Drain 19g voltage Vd is changed, the pinched-off region 15g changes length, but its thin conduction layer is retained, keeping the output impedance high;
- Due to the Gate 17g to channel 15g voltage and the electric field along the conduction channel path (Drain 19g to Source 14g), the conduction channel 15g is forced deeper at the Source 14g and tapers to near pinch-off at the Drain 19g;
- The resulting conduction layer behaves with a Square-law response to the gate voltage at the Gate 17g;
- In strong-inversion, dynamic range of channel current is limited to about 2 or 3 decades; the channel must drop into weak-inversion for additional dynamic range;
- This strong-inversion conduction channel 15g appears as an adjustable current source (high value resistor); and
- The wedge shape of the conduction channel 15g provides high speed from high current density, but requires the carriers to transit the channel and velocity saturation is reached limiting the speed or cutoff frequency of the transistor; and
- This is reflected as the operating point 15h in
FIG. 1hwhich is along its bolded line 18h.
- Strong conduction channel inversion 15g and 15h occurs when the Drain 19g to Source 14g voltage 19h is larger than the threshold Vthreshold 17h in
A two-finger CMOS inverter is illustrated in
- They exist in all logic IC processes
- are the most common and fundamental building block
- highly scalable
- process parameter drift tolerant
- high speed
- high output drive for varying capacitive loads
- arguably the highest gain of a complementary pair of MOS transistors
- low power
- easily used
A basic two finger inverter schematic of the prior art is depicted in
Although similar MOS structures appear in prior art, no significant exploitation of many of its unique properties are known or published. In addition, proper biasing remains as a problem(s) for its operation(s). A deeper understanding of the internal mechanisms resulted in discovery of many desirable applications (enabling superior operation at deep-sub-micron scale), including an approach to proper biasing that takes advantage of natural equilibrium. This natural equilibrium is the result of a “PTAT”/“CTAT” (proportional to absolute temperature/complement to absolute temperature) known as a “Band-Gap” voltage reference mechanism, again functional at deep-sub-micron scale.
Some references show a MOS field effect device includes a body/substrate 16p, the source terminal 14p and drain terminal 19p on the body 16p. The gate terminal 17p is placed between the source terminal 14p and the drain terminal 19p for controlling conductivity therebetween. The device further includes two identical regions 13p and 15p of like “conductivity type” separated by a diffusion region 11p(designated as Z for Low Impedance in the prior art) as shown in
Although a cascode amplifier can be found in prior art, the prior art does not contain a complementary pair of cascode transistors connected as a totem-pole. With this simple compound device structure, feedback from the output to the input can be used to self-bias the resulting inverter into its linear mode. As mentioned above in association with
- Gain of the single stage is maximum when the output is at the midpoint (self-bias point);
- The gain of a single CiFET stage is high (typically approaching 100), therefore, while the final output may swing close to the rails, its input remains near the midpoint where the gain is high.
- When used in a series chain of CiFET devices, all earlier stages operate with their inputs and outputs near the mid-point (“sweet-spot”) where the gain is maximized;
- Slew rate and symmetry are maximized where the channel current is highest (near the mid-point);
- Noise is minimized where the channel current is highest (near the mid-point); and
- Parasitic effects are negligible where the voltage swing is small.
When the gate input signal moves in one direction, the output moves in the inverse direction. For example; a positive input yields a negative output, not so much because the N-channel device is turned on harder, but rather because the P-channel device is being turned off. A Thevenin/Norton analysis perspective shows that the current through the P and N devices must be exactly the same, because there is nowhere else for drain current in one transistor to go except through the drain of the complementary transistor; however the voltage drop across those devices does not have to be equal, but must sum to the power supply voltage. Due to the super-saturated source channel, these voltages are tied together exponentially. This is even more evident at low power supply voltages where the voltage gain peaks due to the conduction channels being forced into a diffusion mode of operation similar to weak-inversion. This means that the gate-to-source voltage is precisely defined by the same and only drain current going through both transistors. Exponentials have the unique transparent physical property like as with a time constant, or “half-life;” It does not matter where a value is at a given point of time, a time constant later the value will be a fixed percentage closer to the final value. This is a “minds-eye” illustration of the primary contributor to output movement in response to input change. This same current balance of gate-to-source operating voltages also indicates why the “sweet-spot” in the self-biased amplifier is so repeatable. In effect it is used as a differential pair-like reference point to the amplifier input signal.
Briefly stated, the operation of the conventional CMOS amplifier of
In operation, differential analog input voltages are applied to Input +10a and Input − 11a of a precisely matched pair of transistors Q1a and Q2a respectively. Any mismatch in these two transistors appears as a DC voltage added to the differential input. If there is 1 millivolt of mismatch, which is very hard to meet in CMOS, and the amplifier has a gain of 1000, the output voltage error will be 1 volt. In newer IC process nodes, power supplies are already limited to less than a volt. Exotic double centroid physical layout with multiple identical transistors arranged in diametrical opposition and everything else possible symmetrically possible are needed in the physical layout of the differential pair to minimize the offset voltage.
These amplifiers function by steering and mirroring bias currents from a current source 12a between their transistors. All the bias currents have to be larger than the peak signal deviations and these currents always flow. These currents also have to be large enough to drive the internal capacitive load of the amplifier'"'"'s internal transistors plus interconnect, not to mention the output drive current which comprises the capacitive load at the maximum bandwidth frequency or slew rate.
The first bias current mirror input transistor is a transistor Q8a which is “diode connected” in that its gate and drain are tied together and bias at a threshold voltage below the top power supply rail. This bias voltage is applied to the gates of two transistors Q5a, Q7a additional positive rail based current mirrors that have to be matched to a lesser degree. In order to progressively increase the mirrored currents from the bias current mirror input transistor Q8a to the differential current feed transistor Q5a to the output pull-up current transistor Q7a, the transistors Q5a and Q7a are actually multiple instances connected in parallel. A double for the transistor Q5a and an eight (8) times for the transistor Q7a are typical choices for these multiples.
The differential pair of the transistors Q1a, Q2a is used to split the bias current to the transistor Q5a equally at the zero differential voltage input where the amplifier strives for. To achieve a voltage gain in analog designs, a positive drive current is balanced against a negative drive current. The differential pair of transistors Q1a, Q2a achieves this by mirroring transistor Q3a of the outputs back to the other leg of transistor Q4a, making current opposition with the transistor Q2a. Voltage gain is gm*RL where RL is the parallel combination of the output impedance of the transistors Q4a and Q2a. For analog MOSFET transistors to present a high impedance on their output, they need to be very long because the depilation width due to drain voltage modifies the conduction channel length near the drain terminal. This is called “channel length modulation” which is similar to the bipolar “Early voltage” named by Jim Early of Fairchild Semiconductor during the early bipolar days. For this high output impedance requirement, the transistor Q4a must be long, and it also must be equally wide to preserve its gain setting the basic transistor sizing of the amplifier. This size must be set equal for the transistors Q3a and Q6a, except the transistor Q6a must also include the multiple used for the transistors Q5a to Q7a along with a factor of two to make up for the split of current by the differential pair. In equilibrium, the gate voltage on the transistor Q6a wants to be the same as the gate voltage on the transistors Q3a, Q4a looking like a pseudo-current mirror arrangement at the bottom power supply rail.
There are still many other linear amplifier circuit design considerations beyond these basic principles like stability considerations by compensation resistance or Rcomp 15a and compensation capacitance or Ccomp 16a and power supply noise rejection. As can easily be envisioned, the design of analog circuits in an IC is quite involved, process parameter dependent, and not very portable between IC processes.
The resulting linearity of these amplifiers are also limited due to different non-linear characteristics between the gain device and the load device (pull-up and pull-down) which cannot cancel each other out. The CiFET device structure, which is the present invention to be explained later in this specification, loads itself with the same device structure, except that the combination obtains its complementary nature through the use of opposite semiconductor diffusion types which inherently and precisely mimic any non-linear characteristics with the opposite sign to cancel each other'"'"'s linearity deviations out. CMOS inverters get their opposing drive through the opposite semiconductor diffusion type, thus are a good foundation to base linearity on. This is because the same current is carried through one transistor is also passed through the complementary device. Inversion is obtained through opposite diffusions.
It is to be noted that during the transition from vacuum tubes to bipolar transistors the industry underwent a major paradigm shift, learning to think in terms of current rather than voltage. With the advent of FETs & MOSFETs the pendulum swing is back toward thinking in terms of voltage, but much knowledge has been lost or forgotten. Herein is contained the rediscovery of some old ideas as well as some new ones, all applied to the up-coming “current” state of the art. It is believed that the inherent simplicity of the present invention speaks to their applicability and completeness.
A first issue may be that there is always a need for a little analog functionality, yet nearly all analog performance metrics of a MOS transistor are remarkably poor as compared to that of a Bipolar transistor. The industry has made MOS devices serve by employing extensive “work-arounds.” Conventional analog design is constrained by one or more of the followings:
- Power supply voltages sufficient to bias the stacked thresholds, and transistors large enough to supply the necessary low output impedance, or high output impedance for gain and linearity.
- Process extensions (unavailable at deep sub-μm scale) to function at all, let alone with the enhanced performance, demonstrated herein.
- Resistors, inductors, and large capacitors are mostly non-existent for analog designs in newer IC processes.
In contrast, bipolar transistors can be made to have high gain (β), wider bandwidth, wider dynamic range (many decades, from near the rails down to the noise floor), better matching (required in differential pairs), and band-gap references. Junction FETs, which operate with sub-surface channel conduction below the surface defects, have lower noise than bipolar transistors. Likewise the iFET super-saturated source channel operates primarily below the defects at the channel surface underneath the gate oxide.
MOS designs are poorer in the above areas but have their own extreme advantages, including, but not limited to:
- MOS devices are small
- highly scalable
- high speed
- low power
- ultra-dense/high functionality systems on a chip, where Bipolar designs cannot go (deep sub-μm scale).
Accordingly, building analog circuits on an IC has always been problematic. Engineering around poorly performing analog components has been the overriding objective for analog IC designers since analog circuits have been integrated. This drove the need for digital signal processing with algorithm development yielding digital magic.
Today the real-world of analog circuit design signals still needs to be converted, on both the front and back end of signal processing systems. This need has become a road-block at deep sub-μm scale.
Another problem may be that solid-state amplifiers have been notoriously non-linear since their inception. To make them linear, increased open loop gain (with levels significantly higher than is ultimately needed) is traded for control over actual circuit gain and linearity through the use of a closed loop (feedback). A closed loop amplifier requires negative feedback. Most amplifier stages are inverting, providing the necessary negative feedback. A single stage, with a closed loop, is stable (does not oscillate). Increased loop gain requires that stages be added such that there are always an odd number of stages (sign is negative), to provide the necessary negative feedback. While a single stage amplifier is inherently stable, three stages and most definitely five stages are unstable (they always oscillate).
The problem then is how to properly compensate a multi-stage closed loop amplifier while maintaining a reasonable gain-bandwidth product. This is particularly difficult at deep-sub-micron scale where circuit stages must be simple in their design. The severely limited power supply voltages preclude the use of conventional analog design approaches. Additionally, it is desirable to avoid reliance upon analog extensions but rather to accomplish the necessary analog functions using all digital parts, to improve yields and decrease costs. Using all digital parts allows analog functions at process nodes that do not yet have analog extensions, and may never have them.
There is a long felt needs for low-cost/high-performance systems on a single chip to realize, affordable high-volume devices such as the Internet of things, smart-sensors, and other ubiquitous devices.
The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of exponential relationships of a super-saturated source channel described in relation to
Through incorporating this compound device structure 200 as shown in
A preferred embodiment of the present invention 300 provides for a stacked pair of transistors with a common gate 301, mirrored with a complementary pair of stacked transistors 302
According to one aspect of the present invention, a CiFET amplifier is provided, which is a basic Analog-in-DIGITAL building block. It is impractical to try to construct analog systems at small scale using the same system design techniques that have been previously applied at larger scales. The power supply voltage is too low to provide a dynamic range needed to swing analog voltages, and the required analog IC process extensions are not available. In the newest ultra-deep sub-μm processes, long and wide transistors are not available, often all the all the individual transistors must be identical in size. The solution is to convert analog signals to digital as early as possible and take advantage of digital signal processing techniques that are available today. To accomplish this it is necessary to have a reliable, precision front-end and that requires a high-precision amplifier. The techniques in this specification point to such a solution.
According to another aspect of the present invention, it takes advantage of the Doping Profile and Ratioing. Not everything in optimizing a circuit has to do with the circuits'"'"' electrical configuration. Proper device sizing and especially coarsely adjusting the size relationship between complementary transistors provides considerable performance benefits. As will be developed in this specification, the CiFET, being a compound device structure, offers extensive opportunity to establish impedance matching and gain control through proper ratio of the physical device parameters. Other important characteristics, like noise, speed, and power, can be tailored through careful specification of the physical construction and doping of the transistors, rather than relying solely on circuit configuration.
According to yet another aspect of the present invention, certain noise advantages are provided. In the end, it comes down to signal-to-noise ratio. Low power supply voltage requirements in ultra-deep-sub-μm IC processes limit the maximum signal swing to a much smaller number than most analog designers are used to. So with a smaller signal, the low-noise techniques embodied herein must be employed in order to maintain the desired signal to noise ratio or perhaps even improve the ratio.
Simply stated, the CiFET device starts with a common 2-finger inverter and re-wires the inverter'"'"'s parallel transistor connections to series, making these intermediate series transistor connections available to spawn a supplementary pair of input/output terminals. These new terminals (referred to as iPorts) are observed to be particularly sensitive to charge transfer (or current) and exhibit ultra-linear analog trans-impedance (input current to output voltage) response, among many other interesting analog properties observed. In a manner similar to an inverter, the output can handle varying high capacitive loads with minor degradation—highly desirable for analog portability. The sizing and rationing of the individual transistor conductance can be roughly optimized to enhance various analog performance metrics.
Traditionally analog MOS circuits convert input voltage to output current (gm), which is then turned back into a voltage by means of an opposing high impedance load; high impedance is needed in order to obtain voltage gain. This results in vastly different gain path verses load path which is made up of nonlinear structures. Thus, a mismatch in output pull-down and pull-up signals come from fundamentally different circuits in order to obtain the signal polarity inversion needed to drive the output up or down. This not only restricts the linearity of the amplification, but the dynamic output swing, and takes appreciable power causing substantial design effort to create at best with poor portable and flawed performance among many other things.
On the other hand, as in a CMOS inverter, the CiFET derives its opposing load by means of opposite diffusion types, not different types of circuits. Both the pull-up and the pull-down circuits are not only the equivalent, but they pass the same current when equilibrium is reached, thus matched circuits passing the same current cancel out nonlinearities leading to minimum distortion over extreme ranges of operation. As in CMOS logic, opposing signals come from opposite diffusion types. In addition the CiFET operates with opposing exponential equalities that enable interesting mathematical operations that are valid over an exciting wide range.
A MOS structure referred to herein as an iFET, where the letter “i” refers to a current and “FET” refers to a Field Effect Transistor, is the enabling element of several high performance and novel designs of the present invention. The present invention is based on the addition of a direct connection to a mid-point in a Field Effect Transistor (or FET) channel and the realization that this is a low impedance port (current port, or herein referred to as “iPort”) having trans-impedance current input to voltage output gain properties realized by providing a bidirectional current sink/source mid-channel with a very low input impedance at a low saturation voltage, and additionally connecting reciprocal iFETs pairs of opposite “conductivity type” or polarity type (P-type & N-type) interconnected to take advantage of their complementary nature to operate as a team and with symmetry to self-bias near the midpoint between power supplies. In addition, the relative conductance of the first and second channels of the iFETs can be adjusted (threshold choice, relative sizing, and doping profiles) to tailor the gain, speed, quiescent current and input impedance of such an complementary iFET (or CiFET) compound device of the present invention.
The iFET, with its iPort provides an uncommon and unexpected solution to the compensation problem, and then continues to provide new or alternative solutions to other old problems, exceeding industry expectations. The advantages of operating circuits in “weak-inversion” have long been known but, so also have the problems. The CiFET enables circuits to exploit the high gain and wider dynamic range available in “weak-inversion,” without sacrificing superior speed performance. The CiFET compound device provides a standard active IC gain device that is superior to ordinary analog MOSETs making digital ICs host analog functionality. It is not a tradeoff.
The following is a list of some of the unusual aspects of a CiFET based circuit, including, but not limited to:
- Operates at low power supply voltage;
- High gain;
- Extremely linear;
- Very high speed (wide band);
- Low noise;
- Quick recovery (DC);
- Uses all digital parts and processes;
- iPorts respond to charge (things in nature are charge based) rather than Volts across a Resistance; and
- iPort has wide dynamic range with constant gain in an open loop.
The gate control terminal 27a or 27b operates like a conventional MOSFET insulated gate, with its high input impedance and a characteristic trans-conductance (gm) transfer function. Typical values of (gm) for a small-signal MOSFET transistor are 1 to 30 millisiemens (1 millisiemen=1/1K-ohm) each, a measure of trans-conductance.
The iPort control terminal 21a or 21b is low impedance with respect to the source terminal 24a or 24b, and has a transfer function that looks more like beta (β) of a bipolar transistor, but is actually trans-resistance (or rm), or more generally, especially at high frequencies, trans-impedance, measured in K-ohms, where the output voltage is a consequence of an input current. Typical resistance values (or values of rm) for a small-signal iFET transistor 200 are 50KΩ to 1MΩ, a measure of trans-resistance. Current input to voltage output (trans-impedance) is the basis for the assertion that 1 uA in will yield an output of 100 mV (or a gain of 100,000:1) at a large signal level, or 1 pA in will yield an output of 100 nanoV (or a gain of 100,000:1) in an LNA (both results from the same circuit).
These values have been shown to remain true for a single minimum sized CiFET, with inputs from 1 pico-ampere to 10 micro-amperes, using the same circuit in simulation and limited device measurements. In 180 nm CMOS construction the noise floor limits measurements below about 10 pico amps. iFETS can be constructed with different length to width proportions with very predictably differing results.
High gain, uncharacteristic or surprising results differing from the state of the art designs, is the result of the “weak-inversion” like exponential characteristics of the source channel 23b of the iFET 200 operating in a highly ionized super-saturation mode 28b.
Speed in this super-saturated source channel 23b is not limited by the transit time of carriers along the source channel 23b, but the high concentration of ionized charge carriers in the active channel only have to push the surrounding charge a little as charge is either added or removed from the source channel 23b by means of the iPort control terminal 21b, resulting in a diffusion current which is defined by exponential relationship as has been realized when a MOSFET is operated in weak-inversion. This is in contrast to an electric field causing the charge to transit the channel, which is a square-law function of the gate control voltage. In this configuration, speed is faster than logic built from the same fundamental transistors and unhampered by the “weak-inversion” stage that has higher gains like bipolar transistors. As opposed to bipolar transistors, control current can go either in or out of the iPort control terminal 21b as well as operate with no iPort current, which is useful for creating a self-bias operating point.
In a self-biased CiFET all of the channels are operated with a higher than normal gate to channel voltage and a lower than normal voltage gradient along the channel. This provides lower noise which is facilitated by the self-biasing approach. The potential at drain terminal 29a or 29b is the same as potential at the gate control terminal 27a or 27b, greatly reducing the pinch-off effect found in conventional analog circuit designs.
The iFET 200, because of the common gate connection over the source channel 23a/23b and drain channel 25a/25b, a higher than conventionally applied voltage is placed on the source channel gate control terminal s27a/s27b (or SG) with respect to the source terminal 24a/24b and source channel 23a/23b when compared to the gate voltage 17e used for weak-inversion 13e of
Trans-resistance (rm) is the “dual” of trans-conductance (gm). When looking up trans-resistance, most of the references are to inductors and capacitors, suggesting that the iFET may be useful in synthesizing inductors. Thus ultra-pure sine-wave oscillators can be made from CiFET stages that do not use inductors.
The iFET works in the following ways: A low noise amplifier requires a low impedance channel. A low impedance channel is low in voltage gain but high in current gain. To establish voltage gain, a second stage, operating as a current to voltage converter, is required. A cascoded pair (one on top of the other) of transistors provides such a configuration. Biasing requirements for a cascoded pair preclude its use at low voltage unless a convenient solution for the biasing problem is found. The CiFET device structure provides the solution to this problem through self-biasing of a complementary pair. The impedance of the source channel 23b can be designed to accommodate the impedance of the particular signal source driving it (see later section on ratio).
Regarding FETs in general, carriers are attracted to the surface by the gate field, a low gate voltage creates a thin surface-layer on the channel (where the conductivity takes place) while a higher gate voltage creates a thicker under-layer. The thin layer of carriers is impeded by the non-uniform surface defects resulting in electrical noise, while a thicker layer of carriers finds a smoother path below the surface, thus reducing total electrical noise. This indicates that higher gate voltage translates to lower noise.
Injection current 20b introduced into the iPort control terminal 21b increases the diffused charge density (number of carriers per volume) throughout the source channel 23b, thus making the source channel 23b even more conductive. The rate of conductivity change is exponential, similar to that found in “weak-inversion.” This exponential rate of conductivity change is due to the low voltage gradient along the source channel 23b (source terminal 24b to iPort control terminal 21b voltage gradient).
The iFET exponential relationship between source channel 23b charge 28b and gate voltage 25b provides access to exponential/logarithmic functionality, where the addition of two logarithmic functions is equivalent to multiplication when an antilog is applied. A reversing antilog or exponential operation recovers the analog output through the opposing complementary CiFET loading device structure. This complement is obtained through opposing diffusion types, similar to CMOS logic, instead of some other transistor linear circuit configuration. Such exponential relationship may be used for various low noise amplifier applications as well as many analog mathematical operations. The exponential relationship is also responsible for the wider dynamic range of these CiFET circuits.
Again, referring to the source region in
The drain channel 25b of the iFET 200 operates more like a conventional FET, in that the thickness of the drain channel 25b is greater near the iPort control terminal 21b (same thickness as the source channel 23b) and tapers as it reaches its diffusion region around the drain terminal 29b (the decreasing voltage differential between drain channel 25b and gate control terminal 27b diminishes the gate 27b to channel 25b field) establishing the output resistance of the transistor as set by the gate voltage Vg. The tapered decreasing channel 25b depth near the drain 29b is from the lower gate 27b to drain 29b voltage which decreases the number of carriers that are ionized up from the semiconductor body 26b below into the conduction channel 25b. When loaded with a complementary iFET, the resulting CiFET device
A thick source conduction channel 23b within the iFET 200, operating at a low voltage gradient along this channel, has a low voltage gain but it has a high power gain as a result of the low input impedance which efficiently accepts input signal energy from the iPort in the form of input current. This source channel also contributes a very minimal noise.
The conduction region 25b around the drain terminal 29b, operating at a higher voltage along its conduction channel 25b, provides the desired voltage gain with a minimal noise contribution when operated with the drain voltage being the same as the gate voltage Vg 27b. This voltage equality is contributed by a unique biasing construct of the CiFET
The iFET 200 of the present invention can be viewed as a differential amplifier (or long tailed pair), as shown in
Regarding the iPort control terminal 21b as shown in
Interestingly, unlike other semiconductor devices, a negative current 20b can be extracted from the iPort 21b, causing a drain (output) 29b shift in the negative direction.
An iFET 200 (as shown in
A P-channel device can be constructed and behaves in a similar fashion to its N-channel counterpart.
It should be emphasized that while the gate input 27a, 27b is inverted with respect to the drain, the iPort 21a, 21b is NOT inverted in EITHER the PiFET or NiFET devices diffusion types with respect to their output drains.
- A small + or − current input on the iPort results in a voltage out that is “K” times larger, but with the same sign as the input.
- 1. “K” does not change over an enormous dynamic range of operation.
- 2. “K” is on the order of 100,000, defined as trans-resistance (rm) and can be viewed as a simple functional block shown in
FIG. 2g. rm units are ohms which is Vout/Iin. rm of FIG. 2grepresents the transfer function of the iPort control terminal of an iFET in accordance with the present invention.
- 3. The rm block in
FIG. 2gis the “dual” of the gm block in FIG. 2f, which defines the normal MOSFET transfer function. Accordingly, current and voltage have been interchanged, and thus rm as shown in FIG. 2gcan be viewed as a simple resistance in ohms, while gm as shown in FIG. 2fis conductance in units of 1/ohms.
- A small + or − current input on the iPort results in a voltage out that is “K” times larger, but with the same sign as the input.
The rm circuit of
The useful power gain is partially realized as current gain. Although MOS circuits are perceived as voltage mode circuits, analog MOS circuits work much better as current or charge controlled circuits. After all MOS transistors operate on the instantaneous charge in their channels and do so with great precision as seen throughout this specification.
- The iPort input terminates in a non-varying, low value resistance (typically 50Ω-50kΩ depending on design). The circuit allows matching an antenna impedance for maximum power transfer into the iPort input.
- The output is a voltage source with a low driving impedance, providing the load with whatever current is required to establish the desired voltage with precision.
Additional iFET observations of the present invention are as follows:
- rm does not change over the entire operating range from near clipping, all the way down to the noise floor. AC performance of an iFET is FLAT from DC to faster than logic speed. Analog voltages only move a little while logic has to get unstuck from one rail and go all the way to the other power supply rail.
- The iPort control terminal, being a current input, is free of voltage derived parasitic effects because the iPort control terminal has very minimal voltage change.
- The iPort termination voltages are either a PTAT or a CTAT (proportional to absolute temperature or the complementary to absolute temperature) bandgap reference depending on the N or P semiconductor diffusion type respectively.
- The output in the complementary CiFET configuration swings around the self-bias midway voltage (“sweet-spot”) between the power supply rails, where it is free of power supply induced noise. Power supply induced noise cancels with this “sweet-spot” as the analog-zero reference.
- The advantages of operating circuits in “weak-inversion” have long been known but, so also have the problems. The iFET enables circuits to exploit the high gain and wide dynamic range available in “weak-inversion,” without sacrificing superior speed performance.
- In the “Behavioral Model”
FIG. 2jthe iPort current is converted to a voltage by a resistance (rm), whose value determines the gain. This “trans-resistance” (rm) is established by the ratio of the “drain channel” to “source channel” conductance, and remains constant throughout the entire operational range. Simulation has shown this resistance (rm) to typically be in the range of 100,000Ω, set by the relative channel sizing. rm is the dual of gm, but with more control.
- a. The output is a low-impedance source follower that can deliver its voltage with all the necessary transient current to drive the next circuit and capacitive load to get there.
- b. The input is a constant low resistance termination (related to rm but much lower) with a constant termination voltage of about 100 mv from the respective power supply rail. This offset voltage is a “bandgap” reference, established by the ratio of the “drain channel” to “source channel” conductance.
The complementary nature of a CMOS inverter of
When sized with similar pull-up conductance to pull-down conductance, the self-bias point is nicely centralized between the power supplies where noise from both the positive and negative power supplies tend to cancel. The variation in process parameters will move this midpoint voltage around a bit, but it is always relative the transistor conductance ratios. At this midpoint, the gain is arguably at the maximum available for the pair of transistors used. In addition, the pull-up performance is equal to the pull-down conductance yielding symmetric DC, AC, and transient response in either direction. The effective threshold voltages cancel each other out in that the circuit always works at its best. The AC bandwidth performance of this conventional inverter is extremely wide as compared to any analog circuit configuration as illustrated in the Bode Plot of AC Gain and Phase in
A primary limiting factor to the use of a logic inverter for an analog voltage amplifier is that the logic inverter has only about 25 db or 18× of voltage gain available with a single inverter stage, as illustrated in the standardized Bode gain-phase plot of
Closed loop analog voltage amplifiers require inverting gain so that the output feedback can move the input back to a virtual ground input voltage. Without the amplifier being inverting, the positive feedback would result in a latched output, like a flip-flop when the feedback loop is closed. Using a series of say three inverters is virtually impossible to stabilize with any frequency response left over in a closed loop application, which is essential for practical analog amplifiers.
While a single iFET has interesting characteristics on its own, a complementary pair of iFETs prove to be much more beneficial. The resulting device is arguably the highest possible power gain and widest bandwidth use of FETs possible.
Essentially, the two pairs of opposite diffusion type transistors 101 and 102 in the inverter device structure 100
These same two pairs of transistors 33d, 35d (or 33e, 35e) and 34d, 36d (34e, 36e) are connected in series in
In many analog circuits, biasing is a problem. Using iFETs in complementary pairs 301 and 302 as shown in
In the “Behavioral Model” of CiFET of the present invention as shown in
The output Voutput 39f is a low-impedance source follower that can deliver its voltage with all the necessary current to drive the next circuit and any capacitive loading in between. The common gate input terminals 30f/30g represent the common gate input terminals 30a/30b/30c/30d/30e of their previous related
The input is a constant low resistance termination (related to rm but much lower) with a constant offset voltage of about 100 mv from the respective power supply rail. This offset voltage is a PTAT/CTAT “bandgap” reference, established by the ratio of the “drain channel” to “source channel” conductance.
A standard CiFET compound device cell can be physically constructed and used like a logic cell for designing analog. Normally this is the only active circuit component needed for analog circuits. Like a transistor, but the CiFET cell does everything needed for an active component.
Now, referring to
How then is the proper bias voltage produced? The simplest way of generating the bias voltage is to use iFETs in complementary pairs 301 and 302, creating an inverting device 300 as shown in
Since the complementary pair 300 of iFETs 301 and 302 is self-biased, any parametric factors are auto-compensated for changes in operating environment. Because of inherent matching between adjacent parts on an IC, the bias generator can be used to bias other iFETs nearby. The real-time self-biasing circuit corrects for parametric changes (in various forms).
Each of the transistors in an inverter of the present invention acts as a “dynamic” load for its complement, allowing the gate voltage to be significantly higher than the traditional bias point of an analog circuit gate. With the complementary iFET compound device'"'"'s higher than normal gate voltage, the source and drain conduction channels are deep, yielding lower noise.
The dominant noise source in a traditional analog circuit is primarily related to the “pinch-off” region near the drain 19g of the conduction channel 15g illustrated in
The operation of the CiFET amplifier differs from the operation of a conventional analog amplifier, with its current mirror loads, in that:
The “Source” channel, as illustrated in the individual iFET
The “Drain” channel 25b operates with its'"'"' Drain terminal 29b at ˜½ Vmax, greatly reducing the pinch-off (and DIBBL) effect. This reduced pinch-off condition is further enhanced by the fact that the “Gate terminal” 27b is operated at ˜½ Vsupply (same as ½ Vmax), meaning no potential difference between the Drain 29b and the Gate 27b. Notice the difference in the thickness between the drain conduction channel 15g in
Another important aspect of the iFET and CiFET compound device is its constant voltage low impedance current input 20b
This subtle but significant difference is one of the enabling features that makes weak-inversion like exponential response work and gives the complementary iFET amplifier its linear response, superior low noise, wider dynamic range, and speed advantages.
MOSFETs do not make particularly good amplifiers compared to equivalent bipolar circuits. They have limited gain, they are noisy, and their high impedance makes them slow. Process parameters are also soft, so that matching a differential input is difficult, unlike bipolar. Bipolar Diff-Amps are developed to the point where the input offset is pretty good, but the move to CMOS never really delivered as good a solution.
It has long been known that superior gain and wide dynamic range performance can be obtained from CMOS operated in weak-inversion. But complications arising from high impedance, due to impractically low currents and high output resistance, preclude taking advantage of the superior gain (equivalent to that of bipolar transistors), dynamic range (exceeding that of bipolar transistors), and logarithmic performance (allowing numerous decades of amplification) that are characteristic of weak-inversion. However, the CiFET conduction channels circumvent these high-impedance limitations of weak-inversion due to the CiFET'"'"'s deep conduction channels 33d, 36d, 33e, 36e
While a MOSFET in weak-inversion, working into a current source load, delivers a logarithmic transfer function, the same MOSFET working into an anti-log load cancels the logarithmic nonlinearity, yielding a precisely linear transfer function. The CiFET amplifier is such a circuit, i.e.: log input, antilog load, yielding perfectly linear, wide dynamic range, low noise, and high speed performance. The low noise is a consequence of the biasing, where the source channel gate potential is unusually high and the potential across the source channel itself is maintained at near zero volts while the voltage across the drain channel is minimized. The drain channel is a level shifter, maintaining a very low voltage on the source channel while delivering high amplitude signal swings at the output with all the output drive to charge any capacitive load. The CiFET is a trans-impedance amplifier
A 3-stage CiFET voltage amplifier delivers an open loop voltage gain of >1 million or 106 which is 120 db and equivalent to 20 bits of digital accuracy, while still maintaining unity gain closed loop stability over its multi-GHz bandwidth. At power supply voltages below 1 volt gains can easily be around 100 million or 108 which is 160 db and equivalent to 27 bits of digital accuracy, while still maintaining unity gain closed-loop stability over its GHz bandwidth, which is obviously limited by the noise floor. It is all about signal to noise. Gain increases as power supply voltage is dropped well below a volt. At a power supply voltage of only 10 millivolts, CiFET current input amplifiers operate with 10 db gain and closed-loop bandwidth over 1 KHz, and can operate at power supply voltages as low as 1.0 millivolt with reasonable performance. Clearly, the CiFET amplifiers are not slaved to the threshold voltage stacking that prior art amplifiers are.
Traditionally engineers have avoided using digital logic in an analog configuration because it was believed to be unacceptably nonlinear and was difficult to bias and impossible to stabilize. Digital logic also sacrifices drive symmetry for compactness. Restoring the symmetry through proper device ratioing (˜3:1 p:n width to ˜4:1 on smaller IC processes) improves linearity, increases noise immunity, and maximizes dynamic range. Self-biasing solves the bias problem.
Noise figures can be particularly optimized on front end amplifiers through proper ratioing. The iFET'"'"'s electrical characteristics can be enhanced by modifying the combined and relative conductance of the source and drain channels, without modifying the available IC process (without analog extensions). When all the transistors must be the same size as in the newest IC processes, multiple transistors can be wired together to achieve the desired iFET rationing, as course resolution works fine. There are several approaches to realizing this optimization (adjusting length, width, and threshold among others).
Nearly any source and drain channel size will make a functional iFET, but varying the individual iFET channel size, both relative and cumulative, increases the iFET performance depending on the objective.
- Lower iPort input impedance is obtained via a lower source channel current density (wider source channel) as compared to the drain channel.
- Higher output voltage gain is obtained via higher source channel current density (narrower source channel) as compared to the drain channel.
- Proportionally sizing the CiFET channel interrelationships optimizes various performance metrics. Gain and symmetry are maximized when the P-channel iFET conductance to N-channel iFET conductance is equalized, thus balancing the CiFET complementary conductance. Equalizing conductance adjusts the self-bias voltage near the midpoint of the power supply voltage. This provides a symmetrical dynamic analog signal range and serves a convenient analog ground or zero reference, permitting “four quadrant” mathematical operations. Experience with deep sub-μm IC processes place the P-channel iFET to be around 3 to 4 times wider than N-channel iFET, as fixed by length or width ratios of the iFET channels.
- The CiFET performance is minimally affected by ambient and IC process parameter variation because of self-biasing to an optimum mid-point, regardless of conditions.
- The power verses speed tradeoff is controlled by the cumulative sum of all of the channel conductances used to set the idle current through the complementary iFET amplifier. This establishes the output slew rate (or output drive capability).
- Care must be exercised so as to not exceed both DC and transient current limitations of the biased CiFET structure. Current rating for the contacts and metal widths must be considered in determining the self-bias current and physical layout care must be considered so as to not be prone to premature failure. Local heating should also be considered.
- Since any logic inverter would work, it is not necessary to even make this optimization, but it is a performance booster.
To be clear, the conductance of the iFET channels are a function of the individual channel width and lengths, as well as their thresholds and doping profiles. Each of the iFET channels can have individually selected sizes and/or threshold relationships to the other related channels.
While iFET amplifiers can be constructed with minimum sized devices which do provide ample current at the output for very fast response and high accuracy, as stated above, care must be exercised so that the complementary iFET amplifier does not pass too much current, subjecting it to mechanical failure. The physical layout requires enough contacts and metal for the required DC and transient currents.
- The CiFET is ratioed to provide a rm gain of 100K;
- Gain remains constant over the entire range;
- Transfer function is precisely linear;
- Plus and minus precisely overlay each other;
- Either iPort input/output precisely overlays the other;
- Input current can be zero;
- Output voltage swings around the midscale AC zero reference voltage,
Also note that the iPort input resistance on the left vertical scale of the graph shown in
The precise linearity of the temperature relationship over an extremely wide temperature range of −150 to +250 degrees Centigrade is plotted in
The AC gain and phase performance of the CiFET device is illustrated by a standardized Bode plot in
Following these three Bode plots are three plots
To make this set of plots easier to comprehend, additional graphs follow each plot in
It has been observed in
This increase in gain with diminishing power supply voltage boosts weak-inversion like operation, where the charge-transport mechanism produces a higher exponential-class of gain. This is also demonstrated with the conventional CMOS inverter of
In the end, it comes down to signal-to-noise ratio. Low power supply voltage requirements in ultra-deep-sub-μm IC processes limit the maximum signal swing to a much smaller number than most analog designers are used to. So with a smaller signal, the noise must be equally small in order to maintain the desired signal to noise ratio. It is imperative that noise issues be reduced. This iFET amplifier technology not only reduces noise by an amount as would be necessary, but performs far beyond expectations, delivering ultra-quiet front ends.
1/f noise in the source channel is reduced because the self-bias scheme provides a high field strength on the source channel'"'"'s gate, forcing carriers in the channel to operate below the surface where there is a smoother path (fewer obstructions) than along the surface where crystal lattice defects interfere.
1/f noise in the drain channel is also low. Unlike conventional analog designs, the gate is self-biased at the half-way point between the power supply rails as is the drain, while the iPort is within ˜100 millivolts of the power rail. With the high electric field along the drain channel, and the gate voltage equal to the drain terminal voltage, the carriers are constrained to flow mostly below the channel surface. This keeps the drain channel out of pinched off conditions, where unwanted 1/f noise would be generated.
Resistance noise is minimized because the self-bias configuration puts the complementary pair at its lowest channel resistance operating point. Resistance noise is caused by collisions, between carriers and the surrounding atoms in the conductor. The lower the resistance is, the fewer the collisions.
Wide band noise (white-noise) would always be an issue in high gain for high frequency circuits. While conventional designs adjust the gate voltage to establish suitable operating point(s), the designs of the present invention establish the gate voltage at the optimum point (the “sweet-spot”) and then adjust the load to establish the desired operating point. This approach establishes a higher quiescent current where (for reasons explained above) higher current density circuits have lower wide band noise.
High common mode power supply rejection is inherent in the complementary iFET device structure of the present invention. Signals are with respect to the mid-point instead of being with respect to one of the power supply rails, similar to an op-amp with its “virtual” ground. Power supply noise is from one rail to the other, equal and opposite in phase with respect to each other; thus canceling around the mid-point.
Ground-Loop noise is diminished because the circuit ground is “virtual” (just like in many op-amp circuits), rather than ground being one or the other power supply connections where ground or power noise is conducted into the analog signal path . . . . In the closed-loop case, “Flying Capacitors” are often employed. With “flying capacitors” there is no direct electrical connection between stages, so there is no common ground; virtual or otherwise. The use of “differential decoupling” (flying capacitors) offers transformer like isolation between stages, with the compactness of integrated circuit elements.
Coupled noise from “parasitic induced crosstalk” increases by the square of the signal amplitude. Unintended capacitive coupling into a 1 volt signal causes a lot more trouble than with a 100 mV signal, by a factor of 100:1 (square law effect). The small low impedance charge or voltage signals employed in the analog sections, reduce this capacitive coupled interference substantially. Nearby Digital signals will, by definition, be high amplitude (rail-to-rail). Good layout practices are still the best defense against this digital source of noise.
There are a number of additional advantages. For example, bi-directional control on the iPort means that current can flow in-to as well as out of this connection; both directions having a significant and symmetrical control effect on overall channel current. Also, a zero current imposed in the iPort is a valid zero input signal, thus the iPort signals are truly bidirectional about zero. The iPort has about five (5) orders of magnitude more dynamic control range than the gate.
When the low impedance iPort is used to measure an analog Signal, the input impedance may diminish the input voltage, but the energy transfer into the iPort amplifier is high, especially for low impedance sources such as matching an antenna, transmission line, or many biological signal sources.
When a high-impedance analog amplifier is necessary, the gate is sued for the input and the amplifier can contain multiple stages for high voltage gain, while the CiFET can stabilize such an amplifier.
In the CiFET device there are two iPort input signals that precisely sum, thus this structure is an analog adder and can combine the two inputs at RF frequencies to form a RF mixer using a single CiFET device.
The iFET of the present invention yields an analog structure that is significantly faster than logic using the same MOS devices. This speed improvement is due to the fact that the complementary structure expresses its maximum gain (and highest quiescent current) at its natural self-bias point, midway between the power supplies.
Since the iPort voltage does not significantly change, it is immune to the R/C time constant effects of the surrounding parasitics, thus the iPort (current) input responds faster than the gate (voltage) input.
When used as a data bus sense amplifier on a RAM, the iPort'"'"'s low impedance rapidly senses minute charge transfer without moving the data bus voltage significantly. Since the iPort input impedance is low, and the iPort is terminated with a fixed low voltage, this sense amplifier approach eliminates the need for pre-charging in the memory readout cycle. Since the iFET operates at better than logic speed, IFET for sensing charge would decrease the readout time impressively.
Since, in most applications of the CiFET compound device structure of the present invention, the output voltage (drain connection point) does not vary greatly, and thus making the output immune to the R/C time constant effects of the surrounding parasitics. A logic signal is slower than analog here because logic signals have to swing from rail to rail.
Drain-induced barrier lowering or (DIBL) threshold reduction is avoided in the CiFET compound device operating in the analog mode. When gain and threshold voltage is important, the drains are operating around half of the power supply voltage, thus eliminating the higher drain voltages where DIBL effects are prevalent.
iFET: A 4 terminal (plus body) device similar to a Field Effect Transistor but with an additional control connection that causes the device to respond to current input stimulus.
source channel: A semiconductor region between iPort diffusion and the Source diffusion. Conduction in this region is enabled by an appropriate voltage on the Gate.
drain channel: A semiconductor region between Drain diffusion and the iPort diffusion. Conduction in this region is enabled by an appropriate voltage on the Gate.
CiInv: A single stage, complementary iFET compound device shown in
super-saturation: an exponential conduction condition similar to weak-inversion, but with high Gate overdrive and forced low voltage along the conduction channel.
feed-forward: A technique to present a signal on an output, early on, in anticipation of the ultimate value.
self-biased: Unlike fixed-bias circuits, self-biased circuits adjust to local conditions to establish an optimum operating point.
dual: (of a theorem, expression, etc.) related to another by the interchange of pairs of variables, such as current and voltage as in “trans-conductance” to “trans-resistance.”
trans-resistance: infrequently referred to as mutual resistance, is the dual of trans-conductance. The term is a contraction of transfer resistance. It refers to the ratio between a change of the voltage at two output points and a related change of current through two input points, and is notated as rm:
The SI unit for trans-resistance is simply the ohm, as in resistance.
For small signal alternating current, the definition is simpler:
trans-conductance is a property of certain electronic components. Conductance is the reciprocal of resistance; trans-conductance is the ratio of the current variation at the output to the voltage variation at the input. It is written as gm. For direct current, trans-conductance is defined as follows:
For small signal alternating current, the definition is simpler:
Trans-conductance is a contraction of transfer conductance. The old unit of conductance, the mho (ohm spelled backwards), was replaced by the SI unit, the siemens, with the symbol S (1 siemens=1 ampere per volt).
translinear circuit: translinear circuit is a circuit that carries out its function using the translinear principle. These are current-mode circuits that can be made using transistors that obey an exponential current-voltage characteristic—this includes BJTs and CMOS transistors in weak-inversion.
Sub-threshold conduction or sub-threshold leakage or sub-threshold drain current is the current between the source and drain of a MOSFET when the transistor is in sub-threshold region, or weak-inversion region, that is, for gate-to-source voltages below the threshold voltage. The terminology for various degrees of inversion is described in Tsividis. (Yannis Tsividis (1999). Operation and Modeling of the MOS Transistor (Second Edition ed.). New York: McGraw-Hill. p. 99. ISBN 0-07-065523-5.)
Sub-threshold slope: In the sub-threshold region the drain current behavior—though being controlled by the gate terminal—is similar to the exponentially increasing current of a forward biased diode. Therefore a plot of logarithmic drain current versus gate voltage with drain, source, and bulk voltages fixed will exhibit approximately log linear behavior in this MOSFET operating regime. Its slope is the sub-threshold slope.
Diffusion current: Diffusion current is a current in a semiconductor caused by the diffusion of charge carriers (holes and/or electrons). Diffusion current can be in the same or opposite direction of a drift current, that is formed due to the electric field in the semiconductor. At equilibrium in a p-n junction, the forward diffusion current in the depletion region is balanced with a reverse drift current, so that the net current is zero. The diffusion current and drift current together are described by the drift-diffusion equation.
Drain-induced barrier lowering: Drain-induced barrier lowering or DIBL is a short-channel effect in MOSFETs referring originally to a reduction of threshold voltage of the transistor at higher drain voltages.
As channel length decreases, the barrier φB to be surmounted by an electron from the source on its way to the drain reduces.
As channel length is reduced, the effects of DIBL in the sub-threshold region (weak-inversion) show up initially as a simple translation of the sub-threshold current vs. gate bias curve with change in drain-voltage, which can be modeled as a simple change in threshold voltage with drain bias. However, at shorter lengths the slope of the current vs. gate bias curve is reduced, that is, it requires a larger change in gate bias to effect the same change in drain current. At extremely short lengths, the gate entirely fails to turn the device off. These effects cannot be modeled as a threshold adjustment.
DIBL also affects the current vs. drain bias curve in the active mode, causing the current to increase with drain bias, lowering the MOSFET output resistance. This increase is additional to the normal channel length modulation effect on output resistance, and cannot always be modeled as a threshold adjustment (Drain-induced barrier lowering—https://en.wikipedia.org/wiki/Drain-induced_barrier_lowering).