COMPENSATION CIRCUIT, GATE DRIVING UNIT, GATE DRIVING CIRCUIT, DRIVING METHODS THEREOF AND DISPLAY DEVICE

• US 20190129562A1
• Filed: 04/30/2018
• Published: 05/02/2019
• Est. Priority Date: 10/31/2017
• Status: Active Grant

• Current Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: LI, Feng, ZHANG, Liang, MA, Yu, SANG, Qi
• Granted Patent: US 10,698,526 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A compensation circuit, a gate driving unit, a gate driving circuit, driving methods thereof and a display device are provided. The compensation circuit includes: a pull-up node voltage control sub-circuit configured to control a first voltage input end to output a first voltage to a pull-up node voltage output end under the control of a control node; and a control node control sub-circuit configured to control a voltage compensation clock signal input end to input a voltage compensation clock signal to the control node under the control of a pull-up input end, control a second voltage input end to input a second voltage to the control node under the control of a voltage compensation resetting end, and control a touch ending signal input end to input a touch ending signal to the control node under the control of a pull-up node voltage output end.

Claims

1. A compensation circuit, comprising a pull-up node voltage output end, a voltage compensation clock signal input end, a touch ending signal input end, a pull-up input end and a voltage compensation resetting end, wherein the compensation circuit further comprises:

a pull-up node voltage control sub-circuit connected to a first voltage input end, a control node and the pull-up node voltage output end, and configured to control the first voltage input end to output a first voltage to the pull-up node voltage output end under the control of the control node; and

a control node control sub-circuit connected to the voltage compensation clock signal input end, the touch ending signal input end, the pull-up input end, the voltage compensation resetting end, the pull-up node voltage output end, the control node and a second voltage input end, and configured to control the voltage compensation clock signal input end to input a voltage compensation clock signal to the control node under the control of the pull-up input end, control the second voltage input end to input a second voltage to the control node under the control of the voltage compensation resetting end, and control the touch ending signal input end to input a touch ending signal to the control node under the control of the pull-up node voltage output end.

2. The compensation circuit according to claim 1, wherein the pull-up node voltage control sub-circuit comprises a first transistor, a gate electrode of the first transistor is connected to the control node, a first electrode of the first transistor is connected to the first voltage input end, and a second electrode of the first transistor is connected to the pull-up node voltage output end.

3. The compensation circuit according to claim 2, wherein the control node control sub-circuit comprises:

a second transistor, a gate electrode of the second transistor is connected to the pull-up input end, a first electrode of the second transistor is connected to the voltage compensation clock signal input end, and a second electrode of the second transistor is connected to the control node;

a third transistor, a gate electrode of the third transistor is connected to the pull-up node voltage output end, and a second electrode of the third transistor is connected to the control node; and

a fourth transistor, a gate electrode of the fourth transistor is connected to the voltage compensation resetting end, a first electrode of the fourth transistor is connected to the control node, and a second electrode of the fourth transistor is connected to the second voltage input end.

4. The compensation circuit according to claim 3, further comprising a fifth transistor, wherein a first electrode of the third transistor is connected to the touch ending signal input end via the fifth transistor, a gate electrode and a first electrode of the fifth transistor are connected to the touch ending signal input end, and a second electrode of the fifth transistor is connected to the first electrode of the third transistor.

5. A gate driving unit comprising a shift register unit circuit and the compensation circuit according to claim 1, wherein the shift register unit circuit comprises a shift resetting end, a shift clock signal input end, a pull-up node, a pull-down node, a gate driving signal output end, a pull-up resetting sub-circuit, a pull-up node control sub-circuit, a pull-down node control sub-circuit, a storage capacitor sub-circuit, an output sub-circuit and an output resetting sub-circuit;

the pull-up node is connected to a pull-up node voltage output end of the compensation circuit;

a pull-up input end of the compensation circuit is connected to a pull-up node of a previous-level gate driving unit;

a voltage compensation clock signal input end of the compensation circuit is connected to a voltage compensation clock signal line for outputting a voltage compensation clock signal;

a voltage compensation resetting end of the compensation circuit is connected to the gate driving signal output end;

a touch ending signal input end of the compensation circuit is connected to a touch ending signal line;

the shift clock signal input end is connected to a shift clock signal line for outputting a shift clock signal;

the pull-up resetting sub-circuit is connected to the shift resetting end, a third voltage input end and the pull-up node, and configured to control the third voltage input end to input a third voltage to the pull-up node under the control of the shift resetting end;

the pull-up node control sub-circuit is connected to the pull-up node, the pull-down node and the third voltage input end, and configured to control the third voltage input end to input the third voltage to the pull-up node under the control of the pull-down node;

the pull-down node control sub-circuit is connected to the pull-up node, the pull-down node, a fourth voltage input end and the third voltage input end, and configured to control a potential at the pull-down node under the control of the pull-up node;

a first end of the storage capacitor sub-circuit is connected to the pull-up node, and a second end of the storage capacitor sub-circuit is connected to the gate driving signal output end;

the output sub-circuit is connected to the gate driving signal output end, the pull-up node and the shift clock signal input end, and configured to control the shift clock signal input end to input a shift clock signal to the gate driving signal output end under the control of the pull-up node; and

the output resetting sub-circuit is connected to the gate driving signal output end, the pull-down node and the third voltage input end, and configured to control the third voltage input end to output the third voltage to the gate driving signal output end under the control of the pull-down node.

6. The gate driving unit according to claim 5, wherein the third voltage is a low voltage, and a fourth voltage from the fourth voltage input end is a high voltage.

7. A gate driving unit comprising a shift register unit circuit and the compensation circuit according to claim 2, wherein the shift register unit circuit comprises a shift resetting end, a shift clock signal input end, a pull-up node, a pull-down node, a gate driving signal output end, a pull-up resetting sub-circuit, a pull-up node control sub-circuit, a pull-down node control sub-circuit, a storage capacitor sub-circuit, an output sub-circuit and an output resetting sub-circuit;

the pull-up node is connected to a pull-up node voltage output end of the compensation circuit;

a pull-up input end of the compensation circuit is connected to a pull-up node of a previous-level gate driving unit;

a voltage compensation clock signal input end of the compensation circuit is connected to a voltage compensation clock signal line for outputting a voltage compensation clock signal;

a voltage compensation resetting end of the compensation circuit is connected to the gate driving signal output end;

a touch ending signal input end of the compensation circuit is connected to a touch ending signal line;

the shift clock signal input end is connected to a shift clock signal line for outputting a shift clock signal;

the pull-up resetting sub-circuit is connected to the shift resetting end, a third voltage input end and the pull-up node, and configured to control the third voltage input end to input a third voltage to the pull-up node under the control of the shift resetting end;

the pull-up node control sub-circuit is connected to the pull-up node, the pull-down node and the third voltage input end, and configured to control the third voltage input end to input the third voltage to the pull-up node under the control of the pull-down node;

the pull-down node control sub-circuit is connected to the pull-up node, the pull-down node, a fourth voltage input end and the third voltage input end, and configured to control a potential at the pull-down node under the control of the pull-up node;

a first end of the storage capacitor sub-circuit is connected to the pull-up node, and a second end the storage capacitor sub-circuit is connected to the gate driving signal output end;

the output sub-circuit is connected to the gate driving signal output end, the pull-up node and the shift clock signal input end, and configured to control the shift clock signal input end to input a shift clock signal to the gate driving signal output end under the control of the pull-up node; and

the output resetting sub-circuit is connected to the gate driving signal output end, the pull-down node and the third voltage input end, and configured to control the third voltage input end to output the third voltage to the gate driving signal output end under the control of the pull-down node.

8. A gate driving unit comprising a shift register unit circuit and the compensation circuit according to claim 3, wherein the shift register unit circuit comprises a shift resetting end, a shift clock signal input end, a pull-up node, a pull-down node, a gate driving signal output end, a pull-up resetting sub-circuit, a pull-up node control sub-circuit, a pull-down node control sub-circuit, a storage capacitor sub-circuit, an output sub-circuit and an output resetting sub-circuit;

the pull-up node is connected to a pull-up node voltage output end of the compensation circuit;

a pull-up input end of the compensation circuit is connected to a pull-up node of a previous-level gate driving unit;

a voltage compensation clock signal input end of the compensation circuit is connected to a voltage compensation clock signal line for outputting a voltage compensation clock signal;

a voltage compensation resetting end of the compensation circuit is connected to the gate driving signal output end;

a touch ending signal input end of the compensation circuit is connected to a touch ending signal line;

the shift clock signal input end is connected to a shift clock signal line for outputting a shift clock signal;

the pull-up resetting sub-circuit is connected to the shift resetting end, a third voltage input end and the pull-up node, and configured to control the third voltage input end to input a third voltage to the pull-up node under the control of the shift resetting end;

the pull-up node control sub-circuit is connected to the pull-up node, the pull-down node and the third voltage input end, and configured to control the third voltage input end to input the third voltage to the pull-up node under the control of the pull-down node;

the pull-down node control sub-circuit is connected to the pull-up node, the pull-down node, a fourth voltage input end and the third voltage input end, and configured to control a potential at the pull-down node under the control of the pull-up node;

a first end of the storage capacitor sub-circuit is connected to the pull-up node, and a second end of the storage capacitor sub-circuit is connected to the gate driving signal output end;

the output sub-circuit is connected to the gate driving signal output end, the pull-up node and the shift clock signal input end, and configured to control the shift clock signal input end to input a shift clock signal to the gate driving signal output end under the control of the pull-up node; and

the output resetting sub-circuit is connected to the gate driving signal output end, the pull-down node and the third voltage input end, and configured to control the third voltage input end to output the third voltage to the gate driving signal output end under the control of the pull-down node.

9. A gate driving unit comprising a shift register unit circuit and the compensation circuit according to claim 4, wherein the shift register unit circuit comprises a shift resetting end, a shift clock signal input end, a pull-up node, a pull-down node, a gate driving signal output end, a pull-up resetting sub-circuit, a pull-up node control sub-circuit, a pull-down node control sub-circuit, a storage capacitor sub-circuit, an output sub-circuit and an output resetting sub-circuit;

the pull-up node is connected to a pull-up node voltage output end of the compensation circuit;

a pull-up input end of the compensation circuit is connected to a pull-up node of a previous-level gate driving unit;

a voltage compensation clock signal input end of the compensation circuit is connected to a voltage compensation clock signal line for outputting a voltage compensation clock signal;

a voltage compensation resetting end of the compensation circuit is connected to the gate driving signal output end;

a touch ending signal input end of the compensation circuit is connected to a touch ending signal line;

the shift clock signal input end is connected to a shift clock signal line for outputting a shift clock signal;

the pull-up resetting sub-circuit is connected to the shift resetting end, a third voltage input end and the pull-up node, and configured to control the third voltage input end to input a third voltage to the pull-up node under the control of the shift resetting end;

the pull-up node control sub-circuit is connected to the pull-up node, the pull-down node and the third voltage input end, and configured to control the third voltage input end to input the third voltage to the pull-up node under the control of the pull-down node;

the pull-down node control sub-circuit is connected to the pull-up node, the pull-down node, a fourth voltage input end and the third voltage input end, and configured to control a potential at the pull-down node under the control of the pull-up node;

a first end of the storage capacitor sub-circuit is connected to the pull-up node, and a second end of the storage capacitor sub-circuit is connected to the gate driving signal output end;

the output sub-circuit is connected to the gate driving signal output end, the pull-up node and the shift clock signal input end, and configured to control the shift clock signal input end to input a shift clock signal to the gate driving signal output end under the control of the pull-up node; and

the output resetting sub-circuit is connected to the gate driving signal output end, the pull-down node and the third voltage input end, and configured to control the third voltage input end to output the third voltage to the gate driving signal output end under the control of the pull-down node.

10. A method for driving the gate driving unit according to claim 5, comprising a step of controlling, by a compensation circuit, a potential at a pull-up node voltage output end under the control of a voltage compensation clock signal input end, a touch ending signal input end, a pull-up input end and a voltage compensation resetting end, so as to control a potential at a pull-up node of a shift register unit circuit of the gate driving unit.

11. The method according to claim 10, comprising:

within an input time period of each display stage, controlling, by a control node control sub-circuit, the voltage compensation clock signal input end to input a voltage compensation clock signal to a control node under the control of a pull-up node of a previous-level gate driving unit, and controlling, by a pull-up node voltage control sub-circuit, a first voltage input end to input a first voltage to the pull-up node voltage output end, under the control of the control node, so as to pull-up a potential at the pull-up node; and

within an output time period of each display stage, controlling, by the shift register unit circuit, the gate driving signal output end to output a corresponding gate driving signal under the control of the pull-up node.

12. The method according to claim 11, wherein each display stage further comprises a resetting time period, and the method further comprises, within the resetting time period, controlling, by the pull-up resetting sub-circuit, a second voltage input end to input a second voltage to the pull-up node under the control of a shift resetting end, so as to reset the potential at the pull-up node.

13. A gate driving circuit, comprising at least one level of the gate driving unit according to claim 5.

14. A gate driving method for use in the gate driving circuit according to claim 13, wherein each driving period comprises a touch stage, and the touch stage comprises a maintenance time period and a voltage compensation time period,

wherein the gate driving method comprises steps of:

entering the touch stage after a corresponding gate driving signal is outputted by a shift register unit circuit of a current-level gate driving unit;

performing a touch scanning operation at the touch stage;

within the maintenance time period of the touch stage, maintaining, by a compensation circuit of a current-level gate driving unit, a potential at a pull-up node of the shift register unit circuit; and

within the voltage compensation time period of the touch stage, charging, by the compensation circuit, a storage capacitor sub-circuit of the shift register unit circuit, so as to pull up the potential at the pull-up node.

15. The gate driving method according to claim 14, wherein each driving period comprises a display stage subsequent to the voltage compensation time period,

wherein the gate driving method further comprises:

at the display stage, stopping the touch scanning operation; and

within a first-row display time period of the display stage, outputting, by the shift register unit circuit, a corresponding gate driving signal again under the control of the pull-up node.

16. The gate driving method according to claim 15, further comprising enabling the gate driving circuit to start and end the touch stage through a shift clock signal line and a touch ending signal line.

17. A display device, comprising the gate driving circuit according to claim 13.