METHOD, DEVICE AND SYSTEM FOR CONTROL SIGNALLING IN A DATA PATH MODULE OF A DATA STREAM PROCESSING ENGINE

• US 20190129720A1
• Filed: 12/14/2018
• Published: 05/02/2019
• Est. Priority Date: 12/29/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ivanov, Vladimir
• Granted Patent: US 10,942,737 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/32 Address formation of the next instruction, e.g. by incrementing the instruction counter G06F9/38 takes precedence
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

Techniques and mechanisms for exchanging control signals in a data path module of a data stream processing engine. In an embodiment, the data path module may be configured to form a set of one or more data paths corresponding to an instruction which is to be executed. In another embodiment, data processing units of the data path module may be configured to exchange one or more control signals for elastic execution of the instruction.

Claims

1. An integrated circuit for operation in a data stream processing engine of an accelerator, the integrated circuit comprising:

multiple data processing units (DPUs) including a read port, a write port, a first data processing unit (DPU) and a second DPU, the multiple DPUs to be programmed to implement a configuration for a data driven execution of an instruction to perform multiple atomic operations, wherein the multiple DPUs to form a set of one or more data paths corresponding to the instruction, wherein the configuration includes;

the read port configured to read into the set of one or more data paths input data to be processed by the data driven execution;

the write port configured to write from the set of one or more data paths a final result of the data driven execution; and

the first DPU configured to exchange with the second DPU both intermediate data based on the input data, the intermediate data for determining the final result, and a first control signal indicating a readiness of the first DPU to perform an action for determining the final result.

2. The integrated circuit of claim 1, wherein the configuration includes the first DPU configured to receive the intermediate data from the second DPU, and the first DPU configured to send the first control signal to the second DPU, and wherein the readiness of the first DPU to perform the action includes a readiness of the first DPU to send a result of a first atomic operation performed with the intermediate data.

3. The integrated circuit of claim 1, wherein the configuration includes the second DPU configured to perform a first atomic operation to generate the intermediate data and to send the intermediate data to the first DPU, and the first DPU configured to send the first control signal to the second DPU, and wherein the readiness of the first DPU to perform the action includes a readiness of the first DPU to receive the intermediate data.

4. The integrated circuit of claim 1, wherein the data driven execution is driven independent of any scheduling signal received by the integrated circuit during the data driven execution.

5. The integrated circuit of claim 1, wherein the set of one or more data paths is to implement an algorithmic loop.

6. The integrated circuit of claim 1, wherein the data driven execution includes the set of one or more data paths operating on address information.

7. The integrated circuit of claim 1, wherein the multiple DPUs to be programmed with a set of control signals sent in parallel each to a respective one of the multiple DPUs.

8. The integrated circuit of claim 1, wherein the instruction is for an algorithm of an algorithm type, and wherein the multiple data processing units (DPUs) include an architecture specific to the algorithm type.

9. The integrated circuit of claim 8, wherein the integrated circuit comprises a programmable switch module including a subset of the multiple DPUs, the programmable switch module providing scarce interconnectivity among DPUs within the architecture specific to the algorithm type.

10. The integrated circuit of claim 1, wherein the multiple DPUs to implement the configuration of the integrated circuit in response to control signals sent to the integrated circuit.

11. The integrated circuit of claim 10, the control signals including information specifying that the first DPU is to perform the first atomic operation.

12. The integrated circuit of claim 1, wherein the multiple DPUs includes one or more of:

a branching unit programmable to determine a branching of data processing in the set of one or more data paths;

a store unit programmable to store data for another DPU; and

a interconnect unit programmable to connect two DPUs.

13. A method at a data stream processing engine (DSPE) of an accelerator, the method including:

receiving a plurality of control signals from a control unit of the data stream processing engine;

programming multiple data processing units (DPUs) of the data path module with the plurality of control signals, the programming the multiple DPUs to implement a configuration for a data driven execution of an instruction which performs multiple atomic operations, wherein the programming the multiple DPUs forms a set of one or more data paths corresponding to the instruction, wherein the configuration includes;

a read port configured to read into the set of one or more data paths input data for processing by the data driven execution;

a write port configured to write from the set of one or more data paths a final result of the data driven execution; and

a first DPU configured to exchange with the second DPU;

intermediate data based on the input data, the intermediate data for determining the final result; and

a first control signal indicating a readiness of the first DPU to perform an action for determining the final result.

14. The method of claim 13, wherein the configuration includes the first DPU configured to receive the intermediate data from the second DPU, and the first DPU configured to send the first control signal to the second DPU, and wherein the readiness of the first DPU to perform the action includes a readiness of the first DPU to send a result of a first atomic operation performed with the intermediate data.

15. The method of claim 13, wherein the configuration includes the second DPU configured to perform a first atomic operation to generate the intermediate data and to send the intermediate data to the first DPU, and the first DPU configured to send the first control signal to the second DPU, and wherein the readiness of the first DPU to perform the action includes a readiness of the first DPU to receive the intermediate data.

16. The method of claim 13, wherein the data driven execution is to be driven independent of any scheduling signal received by the integrated circuit during the data driven execution.

17. The method of claim 13, wherein the set of one or more data paths is to implement an algorithmic loop.

18. The method of claim 13, wherein the data driven execution is to include the set of one or more data paths operating on address information.

19. The method of claim 13, wherein receiving the plurality of control signals includes receiving control signals sent in parallel.

20. The method of claim 13, wherein the instruction is for an algorithm of an algorithm type, and wherein the multiple DPUs include an architecture specific to the algorithm type.