MEMORY SYSTEM AND OPERATING METHOD THEREOF

• US 20190130992A1
• Filed: 07/24/2018
• Published: 05/02/2019
• Est. Priority Date: 10/31/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: WON, Hyung-Sik, KIM, Hyungsup
• Granted Patent: US 10,453,550 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2207/2236 Copy
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/783 with refresh of replacement cells, e.g. in DRAMs
• CPC Class Codes: G11C 29/785 with redundancy programming schemes
• CPC Class Codes: G11C 29/835 with roll call arrangements for redundant substitutions

Abstract

A memory system includes a memory device and a controller. The memory device includes a memory cell array including a normal memory cell area and a redundancy memory cell area, the redundancy memory cell area having a replacement memory cell region and a reserved memory cell region; a register suitable for generating a first signal indicating existence of the reserved memory cell region; and a fuse unit suitable for activating the reserved memory cell region based on the first signal. The controller assigns an address for accessing a reserved memory cell of the reserved memory cell region based on the first signal. A replacement memory cell in the replacement memory cell region replaces a failed memory cell in the normal memory cell region, and the reserved memory cell in the reserved memory cell region remains without replacing any failed memory cell in the normal memory cell region.

Claims

1. A memory system comprising:

a memory device including;

a memory cell array including a normal memory cell area and a redundancy memory cell area, the redundancy memory cell area having a replacement memory cell region and a reserved memory cell region;

a register suitable for generating a first signal indicating existence of the reserved memory cell region; and

a fuse unit suitable for activating the reserved memory cell region based on the first signal; and

a controller suitable for assigning an address for accessing a reserved memory cell of the reserved memory cell region based on the first signal,

wherein a replacement memory cell in the replacement memory cell region replaces a failed memory cell in the normal memory cell region, and the reserved memory cell in the reserved memory cell region remains without replacing any failed memory cell in the normal memory cell region.

2. The memory system of claim 1, wherein the fuse unit stores the address assigned to the reserved memory cell.

3. The memory system of claim 1, wherein the first signal is provided to the fuse unit together with a Mode Register Set (MRS) signal.

4. The memory system of claim 3, wherein the fuse unit activates the reserved memory cell based on the first signal, the MRS signal, and the address assigned to the reserved memory cell.

5. The memory system of claim 1, wherein the controller monitors a number of access requests activating each of a plurality of word lines in the memory device.

6. The memory system of claim 5, wherein the controller controls the memory device to copy data stored in memory cells coupled to a first word line, for which the number of access requests is greater than a threshold value, into memory cells coupled to a second word line of the reserved memory cell region.

7. The memory system of claim 6, wherein the controller assigns an address for activating the first word line to the second word line.

8. The memory system of claim 1, wherein the memory device further includes a memory cell array power management unit that separately manages power of the reserved memory cell region from power of the normal memory cell area.

9. The memory system of claim 8, wherein the memory cell array power management unit turns off the power of the reserved memory cell region unless a request uses the reserved memory cell.

10. The memory system of claim 1, wherein, when a capacity of a memory assigned for processing a request is insufficient, the controller assigns the reserved memory cell to process the request.

11. The memory system of claim 1, wherein, when the memory system includes a plurality of memory devices, the controller controls each of the plural memory devices.

12. An operating method of a memory system, the method comprising:

generating a first signal indicating existence of a reserved memory cell region in a memory cell array included in a memory device;

assigning an address for accessing a reserved memory cell in the reserved memory cell region based on the first signal;

activating the reserved memory cell region based on the first signal; and

controlling the memory device based on the address assigned to the reserved memory cell,

wherein the memory cell array includes a redundancy memory cell area and a normal memory cell area, and

wherein the redundancy memory cell area includes a replacement memory cell region and the reserved memory cell region, the replacement memory cell region including a replacement memory cell for replacing a failed memory cell in the normal memory cell area, the reserved memory cell region including the reserved memory cell that remains without replacing any failed normal memory cell in the normal memory cell area.

13. The method of claim 12, further comprising storing the address assigned to the reserved memory cell.

14. The method of claim 13, wherein the first signal is provided along with a Mode Register Set (MRS) signal.

15. The method of claim 14, wherein the activating of the reserved memory cell region includes activating the reserved memory cell based on the first signal, the MRS signal, and the address assigned to the reserved memory cell.

16. The method of claim 12, further comprising monitoring a number of access requests activating each of a plurality of word lines in the memory device.

17. The method of claim 16, wherein the controlling of the memory device comprises controlling the memory device to copy data stored in memory cells coupled to a first word line, for which the number of access requests is greater than a threshold value, into memory cells coupled to a second word line of the reserved memory cell region.

18. The method of claim 17, further comprising assigning an address for activating the first word line to the second word line.

19. The method of claim 12, further comprising turning off power of the reserved memory cell region unless a request uses the reserved memory cell.

20. The method of claim 14, wherein the controlling of the memory device comprises controlling the memory device to assign the reserved memory cell to process a request when a capacity of a memory assigned for processing the request is insufficient.