INTEGRATED CIRCUIT DIE HAVING BACK-END-OF-LINE TRANSISTORS

• US 20190131437A1
• Filed: 06/30/2016
• Published: 05/02/2019
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: LE, Van Hoang, DEWEY, Gilbert William, RADOSAVLJEVIC, Marko, RIOS, Rafael, KAVALIEROS, Jack T.
• Granted Patent: US 10,644,140 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/8126 Thin film MESFET's
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of-line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.

Claims

1. An integrated circuit die, comprising:

a front-end-of-line (FEOL) portion including a silicon layer having a plurality of transistors, and an insulating layer over the silicon layer; and

a back-end-of-line (BEOL) portion mounted on the insulating layer, the BEOL portion including a non-planar transistor having

an amorphous oxide semiconductor (AOS) channel extending axially from a first end to a second end, and

a gate module extending transversely around the AOS channel at an axial location between a source module at the first end and a drain module at the second end.

2. The integrated circuit die of claim 1, wherein the AOS channel includes an AOS layer between an upper dielectric layer and a lower dielectric layer, and wherein the upper dielectric layer is between an upper metal gate layer and the AOS layer, and the lower dielectric layer is between a lower metal gate layer and the AOS layer.

3. The integrated circuit die of claim 2, wherein the AOS layer includes indium gallium zinc oxide.

4. The integrated circuit die of claim 3, wherein the gate module has a U-shape around the AOS channel

5. The integrated circuit die of claim 4, wherein the AOS channel has a transverse width between respective transverse edges, and wherein the transverse width is at least twice a thickness of the AOS layer.

6. The integrated circuit die of claim 5, wherein the U-shape includes vertical legs separated from the transverse edges of the AOS channel by a transverse gap.

7. The integrated circuit die of claim 3, wherein the metal gate layers extend axially between a first axial edge and a second axial edge, wherein the first axial edge is axially between the source module and the gate module, and wherein the second axial edge is axially between the gate module and the drain module.

8. The integrated circuit die of claim 3, wherein the non-planar transistor includes a stack of AOS channels including the AOS channel and a second AOS channel, wherein the AOS channel is mounted on the FEOL portion and the second AOS channel is mounted on the AOS channel, and wherein the upper metal gate layer of the AOS channel is a lower metal gate layer of the second AOS channel.

9. The integrated circuit die of claim 8, wherein the BEOL portion includes a dielectric layer laterally surrounding the non-planar transistor.

10. An integrated circuit package, comprising:

a package substrate; and

an integrated circuit die mounted on the package substrate, wherein the integrated circuit die includes

a front-end-of-line (FEOL) portion including a silicon layer having a plurality of transistors, and an insulating layer over the silicon layer, and

a back-end-of-line (BEOL) portion mounted on the insulating layer, the BEOL portion including a non-planar transistor having

a stack of amorphous oxide semiconductor (AOS) channels extending axially from a first end to a second end, and

a gate module extending transversely around the stack of AOS channels at an axial location between a source module at the first end and a drain module at the second end.

11. The integrated circuit package of claim 10, wherein the stack of AOS channels includes a plurality of AOS layers between respective upper dielectric layers and lower dielectric layers, and wherein the respective upper dielectric layers are between respective upper metal gate layers and the respective AOS layer, and the respective lower dielectric layer is between a respective lower metal gate layer and the respective AOS layer.

12. The integrated circuit package of claim 11, wherein the plurality of AOS layers include indium gallium zinc oxide.

13. The integrated circuit package of claim 12, wherein the gate module has a U-shape around the stack of AOS channels.

14. The integrated circuit package of claim 12, wherein the stack of AOS channels includes a first AOS channel and a second AOS channel, wherein the first AOS channel is mounted on the FEOL portion and the second AOS channel is mounted on the AOS channel, and wherein a respective upper metal gate layer of the first AOS channel is a respective lower metal gate layer of the second AOS channel.

15. The integrated circuit package of claim 14, wherein the BEOL portion includes a dielectric layer laterally surrounding the non-planar transistor.

16. A method, comprising:

forming an amorphous oxide semiconductor (AOS) channel on a front-end-of-line (FEOL) portion of an integrated circuit die having a plurality of transistors, wherein the AOS channel extends axially from a first end to a second end;

forming a gate module over the AOS channel, wherein the gate module extends around the AOS channel axially between the first end and the second end;

forming a source module over the first end of the AOS channel; and

forming a drain module over the second end of the AOS channel

17. The method of claim 16, wherein forming the AOS channel includes sequentially depositing a lower metal gate layer, a lower dielectric layer, an AOS layer, an upper dielectric layer, and an upper metal gate layer on an insulating layer of the FEOL portion.

18. The method of claim 17, wherein depositing the AOS layer includes depositing indium gallium zinc oxide on the lower dielectric layer.

19. The method of claim 18, wherein forming the AOS channel includes depositing a second AOS channel on the AOS channel, wherein the upper metal gate layer of the AOS channel is a lower metal gate layer of the second AOS channel.

20. The method of claim 19, wherein forming the AOS channel, the gate module, the source module, and the drain module are back-end-of-line processes having thermal budgets less than 500°

C.