BOOST CONTROL SIGNAL GENERATOR

• US 20190131931A1
• Filed: 08/31/2018
• Published: 05/02/2019
• Est. Priority Date: 10/31/2017
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: van Dommelen, Maarten, Chalet, Frederic, Krabbenborg, Benno
• Granted Patent: US 10,454,424 B2
• Time in Patent Office: Days
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 2200/03 the amplifier being designed for audio applications
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/321 Use of a microprocessor in an amplifier circuit or its control circuit
• CPC Class Codes: H03F 3/181 Low-frequency amplifiers, e.g. audio preamplifiers
• CPC Class Codes: H03F 3/183 with semiconductor devices only
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03K 2005/00241 using shift registers
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H04R 3/00 Circuits for transducers , loudspeakers or microphones

Abstract

A method and operates for generating a boost control signal for a DC-DC-booster is described. An audio signal may be received comprising a plurality of audio sample values. The audio signal may be delayed for a delay time. A maximum-delayed-value of the audio sample values during the delay time may be determined. The boost control signal may be generated from the maximum of the non-delayed audio signal sample value and the maximum-delayed-value.

Claims

1. A boost control signal generator for controlling a DC-DC-booster, the boost control signal generator comprising:

a boost control input configured to receive an audio signal comprising a plurality of audio sample values;

a delay line having a delay line input coupled to the boost control input and a delay line output wherein the delay line is configured to output a maximum delayed value of the delayed audio sample values;

a maximum value detector having a first input coupled to the boost control input, a second input coupled to the delay line output and an output coupled to the boost control output, wherein the maximum value detector is configured to output the maximum of the audio sample value and the maximum delayed value.

2. The boost control signal generator of claim 1 wherein the delay line further comprises at least one delay element coupled to the delay stage input, a delay stage maximum value detector having an input coupled to the at least one delay element and an output coupled to the delay line output.

3. The boost control signal generator of claim 1 wherein the delay line comprises a plurality of delay stages arranged between the delay line input and the delay line output, each of the delay-stages including a delay-stage-input, a delay-stage-output and a delay-stage-maximum-value-detector coupled to the respective delay-stage-output;

wherein in operation the sample rate of each delay stage is less than the sample rate of the preceding delay stage.

4. The boost control signal generator of claim 3 wherein each of the plurality of delay-stages comprises at least one delay element, and wherein each delay-stage-maximum-value-detector has at least one input coupled to the at least one delay element output and an input coupled to the delay-stage-input.

5. The boost control signal generator of claim 3 wherein the plurality of delay-stages comprises a first delay-stage and a second delay-stage, wherein the first delay-stage-input is coupled to the delay line input, the first delay-stage-output is coupled to the second delay-stage-input, and the second delay-stage-output is coupled to the delay line output and wherein the second delay stage is configured to down-sample the output of the first delay stage.

6. The boost control signal generator of claim 5 wherein the first delay-stage is configured to receive an audio signal which has been up-sampled by an up-sampling factor, U, and the second delay-stage is configured to operate at the original audio sample frequency.

7. The boost control signal generator of claim 6 wherein the first delay-stage comprises only one delay element, the maximum value detector is arranged to feedback the peak value to the first delay-stage input and wherein the delay element is reset every U cycles.

8. The boost control signal generator of claim 7 wherein the first delay-stage comprises a modulo-U counter coupled to a resettable delay element.

9. The boost control signal generator of claim 1 further comprising an up-sampler having an audio signal input configured to receive an audio signal sampled at a sample frequency and an audio signal output coupled to the delay line input.

10. The boost control signal generator of any claim 9 further comprising an absolute value calculator having an input coupled to the up-sampler output an output coupled tot the delay line input and the maximum value detector input.

11. A DC-DC-boost controller comprising the boost control signal generator of claim 1, wherein the DC-DC-boost controller is configured to vary the dc-supply to an audio amplifier in response to the generated boost control signal.

12. An audio amplifier comprising the DC-DC-boost controller of claim 10.

13. A method of generating a control signal for a DC-DC-boost controller, the method comprising:

receiving an audio signal;

delaying the audio signal for a delay time;

determining a maximum-delayed-value of the audio signal during the delay time; and

determining the maximum of the non-delayed audio signal and the maximum-delayed-value.

14. The method of claim 13 wherein delaying the audio signal further comprises

delaying an audio signal with a plurality of delay stages;

determining a maximum value of the audio signal in each of the delay stages;

providing the determined maximum value of the audio signal in each delay stage to the succeeding delay stage;

and wherein the determined maximum-delayed-value is the determined maximum value of the final delay stage.

15. The method of claim 13 wherein delaying the audio signal comprises storing the audio signal in a memory for at least the delay time.