DATA COMMUNICATION APPARATUS

• US 20190138491A1
• Filed: 11/05/2018
• Published: 05/09/2019
• Est. Priority Date: 11/08/2017
• Status: Active Grant

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Murata Manufacturing Co Limited
• Inventors: NAKAMUTA, Kazuhiro, IIJIMA, Masanori
• Granted Patent: US 10,459,872 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 2213/0016 Inter-integrated circuit (I2C)
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data communication apparatus for performing communication of data with a master device via a bus includes a clock control signal generation circuit that outputs a clock control signal corresponding to a reset state and a communication state of the data communication apparatus, a communication start detection circuit that detects a start of communication on the basis of a clock signal on the bus and the data, a clock generation circuit that generates an internal clock signal on the basis of the clock signal on the bus, and a data processing control circuit that receives the internal clock signal and controls communication of the data with the master device. The clock generation circuit stops generating the internal clock signal in accordance with the clock control signal, in the reset state of the data communication apparatus and in a period from release of the reset state to the start of communication.

Claims

1. A data communication apparatus configured to perform data communication with a master device via a bus, the data communication apparatus comprising:

a clock control signal generation circuit configured to output a clock control signal corresponding to a reset state of the data communication apparatus and a communication state of the data communication apparatus;

a communication start detection circuit configured to detect a start of communication based on a clock signal on the bus and communicated data;

a clock generation circuit configured to generate an internal clock signal based on the clock signal on the bus; and

a data processing control circuit that is supplied with the internal clock signal and that is configured to control data communication with the master device,

wherein the clock generation circuit is configured to stop generating the internal clock signal in accordance with the clock control signal while the data communication apparatus is in the reset state and between an end of the reset state and a start of data communication.

2. The data communication apparatus according to claim 1, further comprising:

a reset circuit configured to output a reset signal for maintaining the reset state when a power supply voltage is less than a predetermined level.

3. The data communication apparatus according to claim 1, wherein when the communicated data satisfies a stop condition for stopping the internal clock signal, the data processing control circuit is configured to generate a stop signal and supply the stop signal to the clock control signal generation circuit.

4. The data communication apparatus according to claim 3, wherein the stop condition is satisfied when a slave address included in the communicated data has a predetermined error pattern.

5. The data communication apparatus according to claim 3, wherein the stop condition is satisfied when read or write data included in the communicated data has a predetermined error pattern.

6. The data communication apparatus according to claim 3, wherein the stop condition is satisfied when an amount of the communicated data exceeds a predetermined level.

7. The data communication apparatus according to claim 3, wherein the stop condition is satisfied when a command included in the communicated data has a predetermined error pattern.

8. The data communication apparatus according to claim 3, wherein, when the data communication apparatus is dynamically assigned an address, the stop condition is satisfied when the data communication apparatus loses arbitration with another data communication apparatus connected to the bus.

9. The data communication apparatus according to claim 3, wherein, when the data communication apparatus is dynamically assigned an address, the stop condition is satisfied when the address assigned to the data communication apparatus has a predetermined error pattern.

10. The data communication apparatus according to claim 3, wherein, when the data communication apparatus is dynamically assigned an address, the stop condition is satisfied when assignment of the address to the data communication apparatus is completed.

11. The data communication apparatus according to claim 3, wherein, when the data communication apparatus makes an interrupt request, the stop condition is satisfied when the data communication apparatus loses arbitration with another data communication apparatus connected to the bus.

12. The data communication apparatus according to claim 3, wherein, when the data communication apparatus makes an interrupt request, the stop condition is satisfied when the interrupt request is rejected by the master device.

13. The data communication apparatus according to claim 3, wherein the stop condition is satisfied when the communicated data is communicated in an operation mode that is not supported by the data communication apparatus.