SYSTEM AND METHOD FOR CIRCUIT SIMULATION BASED ON RECURRENT NEURAL NETWORKS

• US 20190138897A1
• Filed: 04/11/2018
• Published: 05/09/2019
• Est. Priority Date: 11/08/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Xu, Nuo, Jiang, Zhengping, Qi, Weiyi, Wang, Jing, Choi, Woosung
• Granted Patent: US 10,621,494 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06N 3/044 Recurrent networks, e.g. Hopfield networks
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/048 Activation functions
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G06N 3/084 Backpropagation, e.g. using gradient descent

Abstract

According to one embodiment of the present invention a circuit simulator configured to simulate a degraded output of a circuit including a plurality of transistors includes: a behavioral recurrent neural network configured to receive an input waveform and to compute a circuit output waveform; a feature engine configured to model one or more degraded circuit elements in accordance with an aging time, to receive the circuit output waveform and to output a plurality of degraded features; and a physics recurrent neural network configured to receive the plurality of degraded features from the feature engine and to simulate the degraded output of the circuit.

Claims

1. A circuit simulator configured to simulate a degraded output of a circuit comprising a plurality of transistors, the circuit simulator comprising:

a behavioral recurrent neural network configured to receive an input waveform and to compute a circuit output waveform;

a feature engine configured to model one or more degraded circuit elements in accordance with an aging time, to receive the circuit output waveform and to output a plurality of degraded features; and

a physics recurrent neural network configured to receive the plurality of degraded features from the feature engine and to simulate the degraded output of the circuit.

2. The circuit simulator of claim 1, wherein the behavioral recurrent neural network is configured by a plurality of parameters, the parameters being trained in accordance with training data comprising:

an input waveform; and

simulated pristine circuit output waveforms of the circuit in response to the input waveform, simulated by a full circuit simulator.

3. The circuit simulator of claim 1, wherein the feature engine is configured by a plurality of parameters the parameters being trained in accordance with training data comprising simulated device behavior based on reliability models of the transistors of the circuit.

4. The circuit simulator of claim 3, wherein the physics recurrent neural network is configured by a plurality of parameters, the parameters being trained in accordance with training data comprising:

an input waveform;

the degraded features computed by the feature engine; and

simulated degraded circuit output waveforms of the circuit in response to the input waveform at a simulated aging time.

5. The circuit simulator of claim 1, wherein the behavioral recurrent neural network, the feature engine, and the physics recurrent neural network are end-to-end trained by training data, the training data comprising:

an input waveform;

first simulated degraded circuit output waveforms of the circuit in response to the input waveform at a first simulated aging time, simulated by a full circuit simulator; and

second simulated degraded circuit output waveforms of the circuit in response to the input waveform at a second simulated aging time, simulated by the full circuit simulator.

6. The circuit simulator of claim 1, wherein the feature engine comprises a plurality of neurons, each neuron corresponding to one of the transistors of a plurality of representative and critical gates, the plurality of representative and critical gates being selected from among the transistors of the circuit in accordance with a decomposition method.

7. The circuit simulator of claim 1, wherein the feature engine comprises a plurality of neurons, each neuron corresponding to one of the transistors of a plurality of representative and critical gates, the plurality of representative and critical gates being selected from among the transistors of the circuit in accordance with a critical delay path, most degraded gates, or most heavily used gates of the circuit.

8. The circuit simulator of claim 1, wherein the degraded features computed by the feature engine relate to bias-temperature instability, hot carrier injection, and random telegraph noise characteristics of the transistors of the circuit.

9. A method for simulating a degraded output of a circuit comprising a plurality of transistors, the method comprising:

supplying an input waveform to a behavioral recurrent neural network to compute a circuit output waveform;

supplying the circuit output waveform to a feature engine configured to model one or more degraded circuit elements in accordance with an aging time to compute a plurality of degraded features; and

supplying the plurality of degraded features to a physics recurrent neural network to simulate the degraded output of the circuit.

10. The method of claim 9, wherein the behavioral recurrent neural network is configured by a plurality of parameters, the parameters being trained in accordance with training data comprising:

an input waveform; and

simulated pristine circuit output waveforms of the circuit in response to the input waveform, simulated by a full circuit simulator.

11. The method of claim 9, wherein the feature engine is configured by a plurality of parameters, the parameters being trained in accordance with training data comprising simulated device behavior based on reliability models of the transistors of the circuit.

12. The method of claim 11, wherein the physics recurrent neural network is configured by a plurality of parameters, the parameters being trained in accordance with training data comprising:

an input waveform;

the degraded features computed by the feature engine; and

simulated degraded circuit output waveforms of the circuit in response to the input waveform at a simulated aging time.

13. The method of claim 9, wherein the behavioral recurrent neural network, the feature engine, and the physics recurrent neural network are end-to-end trained by training data, the training data comprising:

an input waveform;

first simulated degraded circuit output waveforms of the circuit in response to the input waveform at a first simulated aging time, simulated by a full circuit simulator; and

second simulated degraded circuit output waveforms of the circuit in response to the input waveform at a second simulated aging time, simulated by the full circuit simulator.

14. The method of claim 9, further comprising selecting a plurality of representative and critical gates from among the transistors of the circuit in accordance with a decomposition method,

wherein the feature engine comprises a plurality of neurons, each neuron corresponding to one of the transistors of the plurality of representative and critical gates.

15. The method of claim 9, further comprising selecting a plurality of representative and critical gates from among the transistors of the circuit in accordance with a critical delay path, most degraded gates, or most heavily used gates of the circuit,

wherein the feature engine comprises a plurality of neurons, each neuron corresponding to one of the transistors of the plurality of representative and critical gates.

16. The method of claim 9, wherein the degraded features computed by the feature engine relate to bias-temperature instability and hot carrier injection characteristics of the transistors of the circuit.

17. A system for simulating a degraded output of a circuit comprising a plurality of transistors, the system comprising:

means for computing a circuit output waveform from an input waveform;

means for computing a plurality of degraded features from the circuit output waveform; and

means for simulating the degraded output of the circuit based on the plurality of degraded features.

18. The system of claim 17, wherein the means for computing the circuit output waveform from the input waveform comprises a behavioral recurrent neural network configured by a plurality of parameters, the parameters being trained in accordance with training data comprising:

an input waveform; and

simulated pristine circuit output waveforms of the circuit in response to the input waveform, simulated by a full circuit simulator.

19. The system of claim 17, wherein the means for computing the plurality of degraded features comprises a feature engine configured by a plurality of parameters, the parameters being trained in accordance with training data comprising simulated device behavior based on reliability models of the transistors of the circuit.

20. The system of claim 19, wherein the means for simulating the degraded output of the circuit comprises a physics recurrent neural network configured by a plurality of parameters, the parameters being trained in accordance with training data comprising:

an input waveform;

the degraded features computed by the feature engine; and

simulated degraded circuit output waveforms of the circuit in response to the input waveform at a simulated aging time.

21. The system of claim 17, wherein the means for computing the circuit output waveform, the means for computing the plurality of degraded features, and the means for simulating the degraded output are end-to-end trained by training data, the training data comprising:

an input waveform;

first simulated degraded circuit output waveforms of the circuit in response to the input waveform at a first simulated aging time, simulated by a full circuit simulator; and

second simulated degraded circuit output waveforms of the circuit in response to the input waveform at a second simulated aging time, simulated by the full circuit simulator.

22. The system of claim 17, further comprising means for selecting a plurality of representative and critical gates from among the transistors of the circuit in accordance with a decomposition method,

wherein the means for computing the plurality of degraded features comprises a plurality of neurons, each neuron corresponding to one of the transistors of the plurality of representative and critical gates.

23. The system of claim 17, further comprising means for selecting a plurality of representative and critical gates from among the transistors of the circuit in accordance with a critical delay path, most degraded gates, or most heavily used gates of the circuit,

wherein the means for computing the plurality of degraded features comprises a plurality of neurons, each neuron corresponding to one of the transistors of the plurality of representative and critical gates.

24. The system of claim 17, wherein the degraded features relate to bias-temperature instability and hot carrier injection characteristics of the transistors of the circuit.