Integrated Circuits with Doped Gate Dielectrics

• US 20190139759A1
• Filed: 11/06/2017
• Published: 05/09/2019
• Est. Priority Date: 11/06/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Chung-Liang, Chen, Yen-Yu
• Granted Patent: US 10,522,344 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

Claims

1. A method comprising:

receiving a workpiece that includes a substrate having a channel region;

forming a gate dielectric on the channel region;

forming a first layer on the gate dielectric, wherein the first layer includes tungsten fluoride;

annealing the workpiece to transfer fluorine from the first layer to the gate dielectric; and

removing the first layer after the annealing.

2. The method of claim 1 further comprising:

after the removing of the first layer;

forming a work function layer on the gate dielectric; and

forming a fill material on the work function layer.

3. The method of claim 1 further comprising forming a first capping layer on the gate dielectric such that the first layer is formed on the first capping layer and the annealing of the workpiece transfers the fluorine through the first capping layer.

4. The method of claim 3 further comprising forming a second capping layer on the first capping layer such that the first layer is formed on the second capping layer and the annealing of the workpiece further transfers the fluorine through the second capping layer.

5. The method of claim 1 further comprising forming a blocking layer on the first layer prior to the annealing of the workpiece.

6. The method of claim 1 further comprising:

forming a dummy gate structure on the channel region;

forming gate spacers on side surfaces of the dummy gate structure; and

removing the dummy gate structure such that a trench is defined between the gate spacers, wherein the forming of the gate dielectric forms the gate dielectric within the trench.

7. The method of claim 1, wherein:

the workpiece includes an inter-level dielectric disposed on the substrate; and

the gate dielectric is disposed directly on a top surface of the inter-level dielectric during the annealing.

9. The method of claim 1, wherein the annealing of the workpiece includes performing a rapid thermal anneal at a temperature between about 550°

C. and about 600°

C.

10. The method of claim 9, wherein the rapid thermal anneal is performed for between about 10 second and about 50 seconds.

21. The method of claim 3, wherein the first capping layer includes a metal nitride, and wherein the annealing of the workpiece further transfers nitrogen from the first layer to the gate dielectric.

8. (canceled)

11. A method comprising:

receiving a substrate having;

a pair of source/drain features;

a channel region between the pair of source/drain features; and

a dummy gate structure on the channel region;

removing the dummy gate structure to define a trench over the channel region;

forming a high-k gate dielectric within the trench on the channel region;

forming a layer containing tungsten fluoride on the high-k gate dielectric;

performing a thermal process to transfer the fluorine from the layer to the high-k gate dielectric; and

removing the layer after the performing of the thermal process.

12. The method of claim 11 further comprising forming a gate structure that includes the high-k gate dielectric after the removing of the layer.

13. The method of claim 11, wherein the forming of the layer containing fluorine is performed using an atomic layer deposition process at a deposition temperature between about 300°

C. and about 350°

C. at a pressure between about 5 Torr and about 10 Torr.

14. The method of claim 11, wherein the layer containing tungsten fluoride is formed to a thickness between approximately 10 and 20 Angstroms.

15. The method of claim 11 further comprising forming a blocking layer on the layer containing tungsten fluoride prior to the thermal process.

16. The method of claim 15 wherein the blocking layer includes a material from a group consisting of TiN, SiN, and AlN.

17. A method comprising:

depositing a gate dielectric on a substrate;

depositing a sacrificial layer containing tungsten fluoride on the gate dielectric;

performing an annealing process to transfer fluorine from the sacrificial layer to the gate dielectric;

removing the sacrificial layer; and

forming a gate structure that includes the gate dielectric with the fluorine after the removing of the sacrificial layer.

18. The method of claim 17, wherein the gate dielectric with the fluorine has a fluorine concentration of least 4 atomic percent.

19. The method of claim 17 further comprising forming a first capping layer on the gate dielectric such that the sacrificial layer is formed on the first capping layer and the performing of the annealing process transfers fluorine through the first capping layer.

20. The method of claim 19 further comprising forming a second capping layer on the first capping layer such that the sacrificial layer is formed on the second capping layer and the performing of the annealing process transfers fluorine through the second capping layer.