THREE-DIMENSIONAL MEMORY DEVICE HAVING LEVEL-SHIFTED STAIRCASES AND METHOD OF MAKING THEREOF

• US 20190139974A1
• Filed: 11/07/2017
• Published: 05/09/2019
• Est. Priority Date: 11/07/2017
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: SUGAWARA, Nobutoshi, SUGIHARA, Shigeyuki
• Granted Patent: US 10,629,606 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A plurality of horizontal top surfaces that are vertically offset is formed on a substrate. An alternating stack of insulating layers and spacer material layers is formed and patterned to provide a plurality of staircase regions that are laterally spaced apart and overlies a respective one of the plurality of horizontal top surfaces of the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. A set of contact via cavities are formed over the electrically conductive layers.

Claims

1. A three-dimensional memory device comprising:

a substrate including a plurality of vertically offset horizontal top surfaces, wherein the plurality of top surfaces includes a memory array region horizontal top surface that is located in a memory array region and is more proximal to a back side surface of the substrate than any other of the plurality of horizontal top surfaces located in a contact region;

an alternating stack of insulating layers and electrically conductive layers located over the plurality of horizontal top surfaces and including a plurality of staircase regions, wherein each of the plurality of staircase regions is located over a respective one of the plurality of horizontal top surfaces, and a respective subset of the electrically conductive layers within each of the plurality of staircase regions has a lateral extent that decreases with a vertical distance from the back side surface; and

memory stack structures extending through the alternating stack and located in the memory array region, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel located within the memory film.

2. The three-dimensional memory device of claim 1, wherein the plurality of horizontal top surfaces of the substrate are connected by a respective tapered sidewall, and a respective subset of layers of the alternating stack overlie each of the at least one tapered sidewall.

3. The three-dimensional memory device of claim 2, wherein the plurality of horizontal top surfaces comprises the memory array region horizontal top surface and at least one plateau top surface that is located above a horizontal plane including the memory array region horizontal top surface.

4. The three-dimensional memory device of claim 3, wherein:

the at least one plateau top surface comprises a plurality of plateau surfaces; and

a height of each of the plurality of plateau surfaces from the horizontal plane including the memory array region horizontal top surface increases with a lateral distance from an edge of the memory array region horizontal top surface.

5. The three-dimensional memory device of claim 3, wherein a total number of layers within the alternating stack that overlie the respective tapered sidewall decreases with a lateral distance from an edge of the memory array region horizontal top surface.

6. The three-dimensional memory device of claim 2, wherein:

each neighboring pair of staircase regions is connected by tapered surfaces of the alternating stack that are parallel to the underlying respective tapered sidewall; and

each electrically conductive layer has horizontal and tapered portions in the contact region and has a horizontal strip shape substantially parallel to the memory array region horizontal top surface in the memory array region.

7. The three-dimensional memory device of claim 1, wherein:

the substrate comprises a substrate semiconductor layer; and

each of the plurality of horizontal top surfaces is a top surface of the substrate semiconductor layer.

8. The three-dimensional memory device of claim 1, further comprising at least one semiconductor oxide portion embedded within an upper portion of the substrate, wherein:

at least one of the plurality of horizontal top surfaces is a top surface of the substrate semiconductor layer; and

at least another one of the plurality of horizontal top surfaces is a top surface of the at least one semiconductor oxide portion.

9. The three-dimensional memory device of claim 1, further comprising support pillar structures extending through the alternating stack in the plurality of staircase regions and into an upper portion of the substrate, wherein:

each of the support pillar structures comprises a dummy memory film and a dummy semiconductor channel;

the dummy memory film and the memory film have a same layer composition; and

the dummy semiconductor channel and the semiconductor channel have a same material composition.

10. The three-dimensional memory device of claim 9, wherein the support pillar structures have different heights across the plurality of staircase regions.

11. The three-dimensional memory device of claim 1, further comprising a dielectric material portion continuously overlying the plurality of staircase regions, wherein the dielectric material portion comprises:

a plurality of retro-stepped bottom surfaces contacting a respective stepped surface in a respective one of the plurality of staircase regions; and

at least one tapered bottom surface contacting a respective tapered surface of the alternating stack and located between a neighboring pair of staircase regions among the plurality of staircase regions.

12. The three-dimensional memory device of claim 1, further comprising a set of contact via structures, wherein:

each of the electrically conductive layers is contacted by a respective contact via structures of the set of contact via structures in the contact region; and

a total height variation within the set of contact via structures is equal to, or less than, one half of an entire height of the alternating stack.

13. The three-dimensional memory device of claim 1, wherein:

the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;

the substrate comprises a silicon substrate;

the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;

the electrically conductive layers comprise a plurality of control gate electrodes having a horizontal strip shape extending substantially parallel to the top surface of the substrate in the memory array region, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels located within the memory stack structures, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

14. A method of forming a three-dimensional memory device, comprising:

forming a plurality of vertically offset horizontal top surfaces on a substrate, wherein the plurality of top surfaces includes a memory array region horizontal top surface that is formed in a memory array region and is more proximal to a back side surface of the substrate than any other of the plurality of horizontal top surfaces;

forming an alternating stack of insulating layers and spacer material layers over the plurality of horizontal top surfaces, wherein the spacer material layers are formed as, or are replaced with, electrically conductive layers;

forming a plurality of staircase regions by patterning the alternating stack, wherein each of the plurality of staircase regions is formed over a respective one of the plurality of horizontal top surfaces, and a respective subset of the spacer material layers within each of the plurality of staircase regions has a lateral extent that decreases with a vertical distance from the back side surface; and

forming memory stack structures through the alternating stack in the memory array region, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel located within the memory film.

15. The method of claim 14, wherein:

the substrate comprises a substrate semiconductor layer;

the plurality of horizontal top surfaces is formed by performing at least once a set of processing steps comprising forming a respective patterned photoresist layer outside the memory array region and recessing a respective region of the substrate semiconductor layer that is not masked by the respective patterned photoresist layer; and

the plurality of horizontal top surfaces comprises at least one recessed horizontal surface of the substrate semiconductor layer.

16. The method of claim 15, wherein recessing the respective region of the substrate semiconductor layer forms a respective tapered sidewall of the substrate semiconductor layer that adjoins a recessed horizontal surface of the substrate semiconductor layer.

17. The method of claim 14, wherein:

the plurality of horizontal top surfaces comprises the memory array region horizontal top surface and a plurality of plateau top surface that are located above a horizontal plane including the memory array region horizontal top surface; and

a height of each of the plurality of plateau surfaces from the horizontal plane including the memory array region horizontal top surface increases with a lateral distance from an edge of the memory array region horizontal top surface.

18. The method of claim 14, wherein the plurality of staircase regions is formed by:

applying and pattering a trimming mask layer; and

repeatedly performing a set of processing steps comprising;

an anisotropic etch step in which a respective pair of two topmost layers is anisotropic ally etched within each step area that is not covered by the trimming mask layer; and

a trimming step in which the trimming mask layer is trimmed, thereby providing a respective newly-formed step area that is not covered by the trimming mask layer.

19. The method of claim 14, wherein:

the substrate comprises a substrate semiconductor layer including a continuous horizontal top surface prior to formation of the plurality of horizontal top surfaces;

the method further comprises forming at least one semiconductor oxide portion within an upper portion of the substrate semiconductor layer; and

the plurality of horizontal top surfaces of the substrate comprises top surfaces of the substrate semiconductor layer and a top surface of the at least one semiconductor oxide portion.

20. The method of claim 14, further comprising:

forming a dielectric material portion continuously over the plurality of staircase regions, wherein the dielectric material portion comprises a plurality of retro-stepped bottom surfaces contacting a respective stepped surface in a respective one of the plurality of staircase regions, and at least one tapered bottom surface contacting a respective tapered sidewall of the alternating stack and that is located between a neighboring pair of staircase regions among the plurality of staircase regions; and

forming a set of contact via structures on the electrically conductive layers, wherein each of the electrically conductive layers is contacted by a respective contact via structures of the set of contact via structures in a contact region, and a total height variation within the set of contact via structures is equal to, or less than, one half of an entire height of the alternating stack.