THREE-DIMENSIONAL MEMORY DEVICE HAVING LEVEL-SHIFTED STAIRCASES AND METHOD OF MAKING THEREOF
First Claim
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1. A three-dimensional memory device comprising:
- a substrate including a plurality of vertically offset horizontal top surfaces, wherein the plurality of top surfaces includes a memory array region horizontal top surface that is located in a memory array region and is more proximal to a back side surface of the substrate than any other of the plurality of horizontal top surfaces located in a contact region;
an alternating stack of insulating layers and electrically conductive layers located over the plurality of horizontal top surfaces and including a plurality of staircase regions, wherein each of the plurality of staircase regions is located over a respective one of the plurality of horizontal top surfaces, and a respective subset of the electrically conductive layers within each of the plurality of staircase regions has a lateral extent that decreases with a vertical distance from the back side surface; and
memory stack structures extending through the alternating stack and located in the memory array region, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel located within the memory film.
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Abstract
A plurality of horizontal top surfaces that are vertically offset is formed on a substrate. An alternating stack of insulating layers and spacer material layers is formed and patterned to provide a plurality of staircase regions that are laterally spaced apart and overlies a respective one of the plurality of horizontal top surfaces of the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. A set of contact via cavities are formed over the electrically conductive layers.
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Citations
20 Claims
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1. A three-dimensional memory device comprising:
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a substrate including a plurality of vertically offset horizontal top surfaces, wherein the plurality of top surfaces includes a memory array region horizontal top surface that is located in a memory array region and is more proximal to a back side surface of the substrate than any other of the plurality of horizontal top surfaces located in a contact region; an alternating stack of insulating layers and electrically conductive layers located over the plurality of horizontal top surfaces and including a plurality of staircase regions, wherein each of the plurality of staircase regions is located over a respective one of the plurality of horizontal top surfaces, and a respective subset of the electrically conductive layers within each of the plurality of staircase regions has a lateral extent that decreases with a vertical distance from the back side surface; and memory stack structures extending through the alternating stack and located in the memory array region, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel located within the memory film. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of forming a three-dimensional memory device, comprising:
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forming a plurality of vertically offset horizontal top surfaces on a substrate, wherein the plurality of top surfaces includes a memory array region horizontal top surface that is formed in a memory array region and is more proximal to a back side surface of the substrate than any other of the plurality of horizontal top surfaces; forming an alternating stack of insulating layers and spacer material layers over the plurality of horizontal top surfaces, wherein the spacer material layers are formed as, or are replaced with, electrically conductive layers; forming a plurality of staircase regions by patterning the alternating stack, wherein each of the plurality of staircase regions is formed over a respective one of the plurality of horizontal top surfaces, and a respective subset of the spacer material layers within each of the plurality of staircase regions has a lateral extent that decreases with a vertical distance from the back side surface; and forming memory stack structures through the alternating stack in the memory array region, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel located within the memory film. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification