MULTI-WAFER BASED LIGHT ABSORPTION APPARATUS AND APPLICATIONS THEREOF

• US 20190140133A1
• Filed: 12/13/2018
• Published: 05/09/2019
• Est. Priority Date: 07/24/2015
• Status: Active Grant

• Current Assignee: Artilux, Inc.
• Original Assignee: Artilux Corporation
• Inventors: Chen, Chien-Yu, Cheng, Szu-Lin, Lin, Chieh-Ting, Liu, Yu-Hsuan, Yang, Ming-Jay, Chen, Shu-Lu, Wu, Tsung-Ting, Lin, Chia-Peng
• Granted Patent: US 10,644,187 B2
• Time in Patent Office: Days
• CPC Class Codes: G02B 2006/12061 Silicon
• CPC Class Codes: G02B 6/34 utilising prism or grating G02B6/293 takes precedence
• CPC Class Codes: G02B 6/4204 the coupling comprising intermediate optical elements, e.g. lenses, holograms encapsulated active devices H01S5/02208, H01L33/52
• CPC Class Codes: H01L 27/14629 Reflectors
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 31/02005 for device characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/02161 for devices characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/02327 the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H01L 31/028 including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/0549 comprising spectrum splitting means, e.g. dichroic mirrors
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: H01L 31/107 the potential barrier working in avalanche mode, e.g. avalanche photodiodes
• CPC Class Codes: H01L 31/1812 including only AIVBIV alloys, e.g. SiGe
• CPC Class Codes: H01L 31/1892 methods involving the use of temporary, removable substrates
• CPC Class Codes: Y02E 10/52 PV systems with concentrators
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells

Abstract

Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs'"'"' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.

Claims

1. A method for fabricating a photodetector using a plurality of wafers, the method comprising:

forming, over a first wafer, a first layer including one or more of;

a germanium-based layer, or an aluminum-based layer;

forming, over a second wafer, a second layer including one or more of;

a germanium-based layer, or an aluminum-based layer,

wherein the formed first and second layers include at least one germanium-based layer and one aluminum-based layer; and

performing a wafer bonding process to bond together the first and second wafers, with the formed layers facing each other, wherein at least a portion of the formed layers becomes an aluminum-germanium eutectic alloy that bonds the first and second wafers together;

wherein at least one of said forming steps includes performing one or more pre-bonding processes to its respective layer such that, after said pre-bonding processes, the aluminum-germanium eutectic alloy formed during the wafer bonding process has a lower eutectic temperature than without said pre-bonding processes.

2. The method of claim 1, wherein the eutectic temperature of the aluminum-germanium eutectic alloy ranges from 350 to 400 degrees Celsius.

3. The method of claim 1, wherein the eutectic temperature is lower than a tolerance temperature of a back-end-of-line (BEOL) metal line.

4. The method of claim 3, wherein the tolerance temperature of the BEOL metal line is higher than 420 degrees Celsius.

5. The method of claim 3, wherein the BEOL metal line is an aluminum-based or a copper-based interconnect formed during BEOL semiconductor manufacturing process for a complementary metal oxide semiconductor (CMOS).

6. The method of claim 1, wherein the pre-bonding processes include impurity doping that, depending on a dopant, either enhances or suppresses formation of the aluminum-germanium alloy.

7. The method of claim 1, wherein the pre-bonding processes include doping an enhancement type of dopant into at least one of the formed layers.

8. The method of claim 7, wherein the enhancement type of dopant includes one or more of group-III elements, group-IV elements, or transition metals.

9. The method of claim 7, wherein the enhancement type of dopant includes boron (B), tin (Sn), copper (Cu), gold (Au), or aluminum (Al).

10. The method of claim 1, wherein the pre-bonding processes include doping a suppression type of dopant into at least one of the formed layers.

11. The method of claim 10, wherein the suppression type of dopant includes one or more of group-V elements.

12. The method of claim 10, wherein the suppression type of dopant includes phosphorus (P), arsenic (As), or fluorine (F).

13. The method of claim 1, wherein the pre-bonding processes include impurity doping that, depending on a dopant, either enhances or suppresses formation of the aluminum-germanium alloy, and

wherein the pre-bonding processes further include performing a thermal treatment on a wafer that does not have or has not yet had a semiconductor device formed thereon.

14. The method of claim 1, wherein the pre-bonding processes include impurity doping that, depending on a dopant, either enhances or suppresses formation of the aluminum-germanium alloy, and

wherein the pre-bonding processes further include performing a surface treatment on a wafer that matches a type of the dopant that enhances or suppresses the formation of the aluminum-germanium alloy.

15. The method of claim 14, wherein the surface treatment that matches the type of dopant that enhances the formation of the aluminum-germanium alloy includes a hydrogen containing plasma.

16. The method of claim 14, wherein the surface treatment that matches the type of dopant that suppresses the formation of the aluminum-germanium alloy includes an oxygen containing plasma.

17. The method of claim 1, wherein the pre-bonding treatment processes are selectively applied to some but not all of areas of formed modified layers.

18. The method of claim 1, wherein at least one of the wafers carries a photodetector, and wherein at least a portion of the formed layers that remains after the wafer bonding process functions as an optical structure for the photodetector.

19. The method of claim 1, further comprising:

removing at least a portion of the formed layers that remains after the wafer bonding process,

wherein, after the removing step, the aluminum-germanium eutectic alloy includes a hollow or cavity structure.

20. The method of claim 1, wherein, after the wafer bonding process, the aluminum-germanium eutectic alloy includes a hollow or cavity structure.

21. The method of claim 20, wherein the hollow or cavity structure in the aluminum-germanium eutectic alloy functions as an optical structure.

22. The method of claim 1, further comprising:

forming, over at least one of the formed layers, an additional surface layer that includes one or more of;

crystalline, polycrystalline or amorphous Si, Ge, Sn;

elemental Ni, Ti, Al, W, Cu, Au, Sb, Te, Cd;

compound material TiN, TaN, TiW;

porous dielectrics SiO_x, SiN_x;

or

any combination thereof.

23. A semiconductor manufacturing system having one or more machines, the machines are collectively configured, in fabricating a photodetector using a plurality of wafers, to carry out operations comprising:

forming, over a first wafer, a first layer including one or more of;

a germanium-based layer, or an aluminum-based layer;

forming, over a second wafer, a second layer including one or more of;

a germanium-based layer, or an aluminum-based layer,

wherein the formed first and second layers include at least one germanium-based layer and one aluminum-based layer; and

performing a wafer bonding process to bond together the first and second wafers, with the formed layers facing each other, wherein at least a portion of the formed layers becomes an aluminum-germanium eutectic alloy that bonds the first and second wafers together;

wherein at least one of said forming steps includes performing one or more pre-bonding processes to its respective layer such that, after said pre-bonding processes, the aluminum-germanium eutectic alloy formed during the wafer bonding process has a lower eutectic temperature than without said pre-bonding processes.

24. The system of claim 23, wherein the eutectic temperature of the aluminum-germanium eutectic alloy ranges from 350 to 400 degrees Celsius.