METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR PERFORMING THE SAME

• US 20190146357A1
• Filed: 04/27/2018
• Published: 05/16/2019
• Est. Priority Date: 11/15/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WANG, Wen-Yun, LIN, Hua-Tai, LIU, Chia-Chu
• Granted Patent: US 10,859,924 B2
• Time in Patent Office: Days
• CPC Class Codes: G03F 7/2022 Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: G03F 9/7003 Alignment type or strategy, e.g. leveling, global alignment
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00

Abstract

A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

Claims

1. A method for manufacturing a structure on a substrate, the method comprising:

projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks;

aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern;

obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks; and

determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

2. The method of claim 1, further comprising adjusting, based on the compensation data, a parameter in a tool.

3. The method of claim 2, wherein the tool is an alignment module in a lithography tool.

4. The method of claim 2, further comprising coating a photoresist layer on the first patterned layer.

5. The method of claim 4, further comprising:

after coating the photoresist layer, aligning a photomask to the first patterned layer; and

after aligning the photomask to the first patterned layer, patterning the photoresist layer.

6. The method of claim 5, wherein the parameter is applied in the alignment of the photomask to the first patterned layer.

7. The method of claim 5, further comprising:

prior to pattering the photoresist layer, forming a second material layer between the first patterned layer and the photoresist layer; and

after patterning the photoresist layer, etching the second material layer with the patterned photoresist layer as an etching mask.

8. The method of claim 7, further comprising obtaining an overlay mapping of the first overlay measurement marks and third overlay measurement marks in the etched second material layer.

9. The method of claim 8, further comprising determining another compensation data indicative of information of the overlay mapping of the first overlay measurement marks and the third overlay measurement marks.

10. The method of claim 9, further comprising adjusting, based on the another compensation data, the parameter in the tool or another parameter in the tool.

11. The method of claim 5, further comprising:

generating, based on pattern data, a signal indicative of locations of the second alignment marks, and

in response to the generated signal, adjusting an optical system above the substrate to allow the image of the reference pattern projected onto the substrate to be aligned to the first patterned layer.

12. The method of claim 11, wherein the photomask is manufactured based on the pattern data.

13. The method of claim 4, wherein the photoresist is coated prior to obtaining the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and is exposed after obtaining the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

14. The method of claim 4, wherein the photoresist is coated after obtaining the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and is exposed after obtaining the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

15. The method of claim 2, wherein the tool is one of an e-beam writer, a nano imprinter, or a self-assembling machine.

16. A semiconductor manufacturing tool, comprising:

an alignment tool;

an overlay measurement tool;

a substrate stage on which a substrate having a patterned layer is disposed;

a processor; and

a non-transitory storage medium storing instructions, when executed, causing the processor to;

transmit a signal to the alignment tool to cause the alignment tool to project an image of a reference pattern on the substrate;

cause the alignment tool to perform alignment of the patterned layer to the projected image, based on first alignment marks in the patterned layer and second alignment marks provided by the projected image;

cause the overlay measurement tool to obtain pre-overlay mapping of first overlay measurement marks in the patterned layer and second overlay measurement marks provided by the projected image; and

determine compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

17. The semiconductor manufacturing tool of claim 16, wherein the non-transitory storage medium storing instructions, when executed, further causes the processor to:

transmit a signal indicating the compensation data to another semiconductor tool to cause the another semiconductor tool to adjust a parameter in response to the received signal.

18. The semiconductor manufacturing tool of claim 16, further comprising an exposure tool,

wherein the non-transitory storage medium storing instructions, when executed, further causes the processor to:

adjust a parameter of the alignment tool;

after adjusting the parameter of the alignment tool, cause the alignment tool to re-perform alignment of the patterned layer to the projected image; and

after re-performing the alignment, cause the exposure tool to expose a photoresist layer coated on the patterned layer.

19. A semiconductor manufacturing system, comprising:

a virtual alignment and pre-overlay measurement tool configured to;

project an image of a reference pattern onto a substrate,

virtually align a first patterned layer to the projected image based on first alignment marks in the first patterned layer and second alignment marks provided by the projected image,

obtain a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and

determine compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks;

an alignment and exposure tool configured to;

align a photomask to the first patterned layer based on the compensation data, and expose a photoresist layer coated on the first patterned layer; and

an developing tool configured to develop the exposed photoresist layer.

20. The semiconductor manufacturing system of claim 19, wherein among the virtual alignment and pre-overlay measurement tool and the alignment and exposure tool, only the alignment and exposure tool comprises a radiation source for exposing the photoresist layer.