Static Random Access Memory (SRAM) Tracking Cells and Methods of Forming the Same

• US 20190147945A1
• Filed: 12/21/2018
• Published: 05/16/2019
• Est. Priority Date: 01/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy
• Granted Patent: US 10,643,688 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G

Abstract

An embodiment static random access memory (SRAM) array includes a writable SRAM cell disposed in a first row of the SRAM array and an SRAM read current tracking cell in the first row of the SRAM array. The SRAM current tracking cell includes a first read pull-down transistor and a first read pass-gate transistor. The first read pull-down transistor includes a first gate electrically connected to a first positive supply voltage line; a first source/drain electrically connected to a first ground line; and a second source/drain. The first read pass-gate transistor includes a third source/drain electrically connected to the second source/drain and a fourth source/drain electrically connected to a read tracking bit line (BL). The read tracking BL is electrically connected to a read sense amplifier timing control circuit.

Claims

1. A memory array comprising:

a first plurality of writable memory cells; and

a first cell comprising;

a first pair of cross-coupled inverters;

a first transistor connected to a first node of the first pair of cross-coupled inverters, wherein a voltage applied to a gate of the first transistor is directly tied to a voltage of a first supply voltage line; and

a second transistor, wherein the first transistor serially connects the second transistor to a first ground line, wherein the second transistor comprises a source/drain connected to a read tracking bit line (BL), and wherein the read tracking BL is connected to a read sense amplifier (SA) timing control circuit of the memory array.

2. The memory array of claim 1, wherein the first cell is in a same row of the memory array as the first plurality of writable memory cells, wherein the memory array further comprises:

a second plurality of writable memory cells; and

a second cell in a same row of the memory array as the second plurality of writable memory cells, wherein the second cell is in a same column of the memory array as the first cell, and wherein the second cell has a different circuit layout than the first cell.

3. The memory array of claim 2, wherein the second cell comprises:

a second pair of cross-coupled inverters;

a third transistor; and

a fourth transistor, wherein the third transistor serially connects the fourth transistor to the first ground line, and wherein the fourth transistor comprises;

a gate connected to a second ground line; and

a source/drain connected to the read tracking BL.

4. The memory array of claim 3, wherein the first ground line and the second ground line are on opposing sides of the read tracking BL.

5. The memory array of claim 2, wherein the memory array further comprises a third cell in a same column of the memory array as the first cell and the second cell, wherein the second cell is between the first cell and the third cell, and wherein the third cell has a same circuit layout as the first cell.

6. The memory array of claim 2, wherein the memory array further comprises a third cell in a same column of the memory array as and adjacent to the first cell, and wherein the third cell has a same circuit layout as the first cell.

7. The memory array of claim 6, wherein the memory array further comprises a fourth cell in a same column of the memory array as and adjacent to the second cell, and wherein the fourth cell has a same circuit layout as the second cell.

8. The memory array of claim 1 further comprising:

a fifth transistor connected to a second node of the first pair of cross-coupled inverters; and

a write tracking BL connected to a source/drain of the fifth transistor, wherein the write tracking BL is connected to a write SA timing control circuit of the memory array.

9. A memory array comprising:

a first plurality of writable memory cells; and

a first cell in a same row of the memory array as the first plurality of writable memory cells, the first cell comprising;

a first pair of cross-coupled inverters;

a first transistor connected to an output of the first pair of cross-coupled inverters;

a second transistor, wherein the first transistor serially connects the second transistor to ground, wherein the second transistor comprises;

a gate, wherein a voltage applied to the gate of the second transistor is directly tied to a voltage of a first ground line; and

a source/drain connected to a read tracking bit line (BL), wherein the read tracking BL is connected to a read sense amplifier (SA) timing control circuit of the memory array.

10. The memory array of claim 9 further comprising:

a second plurality of writable memory cells; and

a second cell in a same cell in a same row of the memory array as the second plurality of writable memory cells, the second cell comprising;

a second pair of cross-coupled inverters;

a third transistor, wherein a voltage applied to a gate of the third transistor is directly tied to a voltage of a first supply voltage line; and

a fourth transistor, wherein the third transistor serially connects the fourth transistor to a second ground line, wherein the fourth transistor comprises a source/drain connected to the read tracking BL.

11. The memory array of claim 10 further comprising:

a fifth transistor connected to a node of the second pair of cross-coupled inverters; and

a write tracking BL connected to a source/drain of the fifth transistor, wherein the write tracking BL is connected to a write SA timing control circuit of the memory array.

12. The memory array of claim 11, wherein the write tracking BL is between the first supply voltage line and the first ground line.

13. The memory array of claim 10, wherein the first supply voltage line has a greater width than the first ground line.

14. The memory array of claim 9, wherein first transistor shares a gate structure a pair of transistors of the first pair of cross-coupled inverters.

15. The memory array of claim 9, wherein the first transistor and the second transistor share a source/drain region.

16. A memory array comprising:

a first inverter comprising a first transistor and a second transistor sharing a first gate electrode;

a third transistor sharing the first gate electrode with the first transistor and the second transistor, the third transistor comprising a first source/drain region electrically connected to a first ground line; and

a fourth transistor sharing a second source/drain region with the third transistor, wherein the fourth transistor comprises a second gate electrode and a third source/drain region, and wherein the second source/drain region is between the first gate electrode and the second gate electrode;

a first gate contact electrically connecting the second gate electrode to a second ground line; and

a first source/drain contact electrically connecting the third source/drain region to a first tracking bit line (BL), wherein the tracking BL is electrically connected to a sense amplifier (SA) timing control circuit.

17. The memory array of claim 16, wherein the tracking BL is between the first ground line and the second ground line.

18. The memory array of claim 16, wherein the tracking BL extends directly over the first gate electrode and the second gate electrode.

19. The memory array of claim 16, further comprising a second tracking bit BL on an opposing side of the first ground line opposite tracking BL.

20. The memory array of claim 16, wherein a second source/drain region of the first transistor is electrically connected to the first ground line.