RLINK-ON-DIE INTERCONNECT FEATURES TO ENABLE SIGNALING

• US 20190148227A1
• Filed: 07/02/2016
• Published: 05/16/2019
• Est. Priority Date: 07/02/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: ZHANG, Yu Amos, AYGUN, Kemal
• Granted Patent: US 10,886,171 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645

Abstract

Integrated circuit (IC) chip “on-die” interconnection features (and methods for their manufacture) may improve signal connections and transmission through a data signal communication channel from one chip, through semiconductor device packaging, and to another component, such as another chip. Such chip interconnection features may include (1) “last silicon metal level (LSML)” data signal “leadway (LDW) routing” traces isolated between LSLM isolation (e.g., power and/or ground) traces to: (2) add a length of the isolated data signal LDW traces to increase a total length of and tune data signal communication channels extending through a package between two communicating chips and (3) create switched buffer (SB) pairs of data signal channels that use the isolated data signal LDW traces to switch the locations of the pairs data signal circuitry and surface contacts for packaging connection bumps.

Claims

1. An integrated circuit chip comprising:

a data signal circuit disposed on a horizontal inner level within the chip;

a data signal surface contact disposed on an exposed horizontal surface of the chip;

a data signal leadway (LDW) trace vertically disposed on a LDW trace horizontal level of the chip between the horizontal inner level and the exposed horizontal surface;

the data signal LDW trace having a first end, a second end opposite the first end, and a horizontal length between the first end and the second end;

the first end coupled to the circuit and the second end coupled to the surface contact, wherein the length is between 50 um and 500 um.

2. The chip of claim 1, wherein the data signal LDW trace is disposed within a horizontal last silicon metal level (LSML) of the chip.

3. The chip of claim 1, further comprising:

a first via contact vertically attaching the data signal circuit to the first end of the data signal LDW trace; and

a second via contact vertically attaching the data signal surface contact to the data signal LDW trace.

4. The chip of claim 1, wherein the data signal LDW trace has a width between 2 um and 4 um;

and a height of between 2 um and 4 um.

5. The chip of claim 1, wherein the data signal LDW trace is a first data signal LDW trace having a horizontal first length between its first end and second end, and further comprising:

a second data signal LDW trace vertically disposed on the LDW trace horizontal level of the chip;

the second data signal LDW trace having a first end, a second end opposite the first end, and a second horizontal length between the first end and the second end;

wherein the second length is between 50 um and 500 um;

an isolation signal LDW trace vertically disposed on the LDW trace horizontal level of the chip;

the isolation signal LDW trace having a first end, a second end opposite the first end, and a third horizontal length between the first end and the second end;

the isolation signal LDW trace horizontally disposed on the LDW trace level between the first data signal LDW trace and the second data signal LDW trace.

6. The chip of claim 5, the first data signal LDW trace, the second data signal LDW trace, and the isolation signal LDW trace all extending parallel to each other on the LDW trace horizontal level of the chip.

7. The chip of claim 5, the first data signal LDW trace, the second data signal LDW trace, and the isolation signal LDW trace all having the same length and are all disposed within a horizontal last silicon metal level LSML of the chip.

8. The chip of claim 5, the isolation signal LDW trace is disposed within the chip at a location to electronically shield data signals on the first data signal LDW trace from data signals on the second data signal LDW trace.

9. The chip of claim 4, further comprising:

an isolation signal trace disposed on a horizontal level within the chip;

an isolation signal surface contact disposed on the exposed horizontal surface of the chip;

the first end of the isolation LDW trace coupled to the isolation trace and the second end of the isolation LDW trace coupled to the isolation surface contact, wherein the third length is between 50 um and 500 um.

10. The chip of claim 4, wherein the data signal circuit is a first data signal circuit, and wherein the data signal surface contact is a first data signal surface contact, and further comprising:

a second data signal circuit disposed on the horizontal inner level within the chip;

a second data signal surface contact disposed on the exposed surface of the chip;

the first end of the second data LDW trace coupled to the second data isolation trace and the second end of the second data LDW trace coupled to the second data surface contact.

11. The chip of claim 10, further comprising:

wherein the first data signal circuit is horizontally disposed at a first X,Y location of the chip and is vertically on the inner level within the chip;

wherein the second data signal circuit is horizontally disposed at a second X,Y location of the chip and is vertically on the inner level within the chip;

wherein the first data signal surface contact is horizontally disposed at the second X,Y location of the chip and is vertically on the surface of the chip; and

wherein the second data signal surface contact is horizontally disposed at the first X,Y location of the chip and is vertically on the surface of the chip.

12. The chip of claim 11, wherein the LDW trace horizontal level is a first LDW trace horizontal level, and further comprising:

a third and fourth data signal circuit disposed on the inner level;

a third and fourth data signal surface contact disposed on the exposed surface;

a third and fourth data signal LDW trace vertically disposed on a second LDW trace horizontal level;

the third and fourth data signal LDW trace having a first end, a second end opposite the first end, and a length between the first end and the second end;

the first end coupled to the third and fourth circuit and the second end coupled to the third and fourth surface contact;

wherein the third data signal circuit is horizontally disposed at a third X,Y location of the chip and is vertically on the inner level within the chip;

wherein the fourth data signal circuit is horizontally disposed at a fourth X,Y location of the chip and is vertically on the inner level within the chip;

wherein the third data signal surface contact is horizontally disposed at the fourth X,Y location of the chip and is vertically on the surface of the chip; and

wherein the fourth data signal surface contact is horizontally disposed at the third X,Y location of the chip and is vertically on the surface of the chip.

13. The chip of claim 12, wherein the first and second locations are horizontally widthwise offset from the third and fourth locations by a pitch width of the surface contacts;

and wherein the first and second locations are horizontally lengthwise offset from the third and fourth locations by half a pitch length of the surface contacts.

14. The chip of claim 1, wherein the data signal circuit is a data signal transmitter circuit, wherein the data signal surface contact is a data signal transmit surface contact, and wherein the transmit data signal LDW trace is a transmit data signal LDW trace.

15. The chip of claim 1, wherein the data signal circuit is a data signal receiver circuit, wherein the data signal surface contact is a data signal receive surface contact, and wherein the transmit data signal LDW trace is a receive data signal LDW trace.

16. The chip of claim 1, wherein the integrated circuit chip is a first integrated circuit chip, wherein the data signal circuit is a data signal transmitter circuit, wherein the data signal surface contact is a data signal transmit surface contact, and wherein the transmit data signal LDW trace is a transmit data signal LDW trace having a horizontal first length between its first end and second end, and further comprising:

a second integrated circuit chip having;

a data signal receiver circuit disposed on a horizontal inner level within the second chip;

a data signal receive surface contact disposed on an exposed horizontal surface of the second chip;

a receive data signal LDW trace vertically disposed on an LDW trace horizontal level of the second chip;

the receive data signal LDW trace having a first end, a second end opposite the first end, and a horizontal second length between its first end and second end;

its first end coupled to the receive circuit and its second end coupled to the receive surface contact of the second chip; and

a chip package electrically coupling the data signal transmit surface contact of the first chip to the data signal receive surface contact of the second chip.

17. An integrated circuit chip comprising:

a first data signal circuit disposed on a horizontal inner level within the chip;

a first data signal surface contact disposed on an exposed horizontal surface of the chip;

a first data signal leadway (LDW) trace vertically disposed on a LDW trace horizontal level of the chip between the horizontal inner level and the exposed horizontal surface;

the first data signal LDW trace having a first end, a second end opposite the first end, and a horizontal length between the first end and the second end;

the first end coupled to the first circuit and the second end coupled to the first surface contact;

a second data signal LDW trace vertically disposed on the LDW trace horizontal level of the chip;

the second data signal LDW trace having a first end, a second end opposite the first end, and the horizontal length between the first end and the second end; and

an isolation signal LDW trace vertically disposed on the LDW trace horizontal level of the chip;

the isolation signal LDW trace having a first end, a second end opposite the first end, and the horizontal length between the first end and the second end;

the isolation signal LDW trace horizontally disposed on the LDW trace level between the first data signal LDW trace and the second data signal LDW trace, wherein the length is between 50 um and 500 um.

18. The chip of claim 17, the first data signal LDW trace, the second data signal LDW trace, and the isolation signal LDW trace all extending parallel to each other on the LDW trace horizontal level of the chip.

19. The chip of claim 18, wherein the first data signal LDW trace, the second data signal LDW trace and the isolation signal LDW trace all extending parallel to each other within a horizontal last silicon metal level (LSML) of the chip.

20. An electronic system comprising:

a first integrated circuit chip having;

a data signal transmitter circuit disposed on an inner level within the first chip;

a data signal transmit surface contact disposed on an exposed surface of the first chip;

a transmit data signal LDW trace having a first end, a second end opposite the first end, and a first length between its first end and its second end;

the first end coupled to the transmitter circuit and the second end coupled to the transmit surface contact of the first chip;

a second integrated circuit chip having;

a data signal receive circuit disposed on an inner level within the second chip;

a data signal receive surface contact disposed on an exposed surface of the second chip;

a receive data leadway (LDW) trace having a first end, a second end opposite the first end, and a second length between its first end and its second end;

the first end coupled to the receive circuit and the second end coupled to the receive surface contact of the second chip; and

a chip package electrically coupling the data signal transmit surface contact of the first chip to the data signal receive surface contact of the second chip.

21. The system of claim 20, the chip package further comprising:

a data signal transmit surface contact disposed on an exposed surface of the package at a first horizontal location of the package, the data signal transmit surface contact of the package attached to the data signal transmit surface contact of the first chip;

a data signal receive surface contact disposed on an exposed surface of the package at a second horizontal location of the package, the data signal receive surface contact of the package attached to the data signal receive surface contact of the second chip;

a data signal package trace attaching the data signal transmit surface contact of the package to the data signal receive surface contact of the package, the data signal package trace having a third length.

22. The chip of claim 21, wherein a data signal channel comprises at least the transmit data signal LDW trace, the data signal package trace and the receive data signal LDW trace;

and a channel length comprises at least the first length, plus the second length, plus the third length;

and wherein the channel length is tuned to increase eye height for high speed data signals transmitted on the channel from the transmit circuit to the receive circuit.

23. The chip of claim 22, wherein the first and second length are each between 50 um and 500 um;

and the third length is between 3 and 6 mm.