NAND FLASH MEMORY DEVICE HAVING FACING BAR AND METHOD OF FABRICATING THE SAME

• US 20190148388A1
• Filed: 12/15/2017
• Published: 05/16/2019
• Est. Priority Date: 11/15/2017
• Status: Active Grant

• Current Assignee: Dosilicon Co., Ltd.
• Original Assignee: Dosilicon Co., Ltd.
• Inventors: KIM, Jin Ho, KANG, Tae Gyoung
• Granted Patent: US 10,461,091 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A NAND flash memory device having a facing bar and a method of fabricating the same are provided. The method includes forming one transistor or a plurality of stack transistors as cell transistors on two side surfaces of a facing bar to have transmission channels thereat. In this case, the height of the facing bar may be easily increased. Thus, not only a layout area of unit transistors including the cell transistors but also a layout area of cell strings may be minimized, and lengths of the transmission channels of the cell transistors may be sufficiently extended. As a result, according to the NAND flash memory device and the method of fabricating the same, the overall operating characteristics are improved.

Claims

1. A NAND flash memory device comprising:

a facing bar configured to protrude to have a predetermined width and height from a planar surface of a semiconductor substrate and configured to extend in a first direction which is a horizontal direction with respect to a horizontal surface of the semiconductor substrate, the facing bar being divided into a plurality of device forming sections by a plurality of active regions, wherein the plurality of active regions extend parallel with one another in a second direction of the horizontal direction and are electrically isolated from one another, and the second direction intersects the first direction; and

a first side structure and a second side structure provided on two side surfaces of the facing bar, each of the first side structure and the second side structure including a base electrode guard including a conductive material, the base electrode guard extending in the first direction to be provided on the plurality of active regions, wherein the first side structure and the second side structure are divided into a plurality of first active structures and a plurality of second active structures to correspond to the plurality of device forming sections,

wherein each of the plurality of first active structures and the plurality of second active structures comprises a base transistor in which at least a portion of a base transmission channel is provided on a side surface of the facing bar according to a voltage applied to a control gate, and the control gate is provided as a portion of the base electrode guard,

wherein the base transistor of the first active structures and the base transistor of the second active structures, which correspond to one of the device forming sections, are provided as a portion of one cell string.

2. The device of claim 1, wherein the base transmission channel of the base transistor is provided on the side surface of the facing bar and the planar surface of the semiconductor substrate.

3. The device of claim 1, wherein each of the first side structure and the second side structure further comprises a base trap guard provided between the base electrode guard and the side surface of the facing bar to extend in the first direction, and configured to trap charges,

wherein the base transistor is a trap transistor having a trap gate provided as a portion of the base trap guard.

4. The device of claim 1, wherein each of the plurality of first side structures and the plurality of second side structures further comprises:

a stack electrode guard including a conductive material and provided on the base electrode guard to extend in the first direction; and

a stack trap guard provided between the stack electrode guard and the side surface of the facing bar to extend in the first direction, the stack trap guard capable of trapping charges,

wherein each of the plurality of first active structures and the plurality of second active structures further comprises a stack transistor in which a stack transmission channel is provided on the side surface of the facing bar according to a voltage applied to a control gate, and the control gate is provided as a portion of the stack electrode guard,

wherein the stack transistor is a trap transistor that is connected in series to the corresponding base transistor and provided as a portion of the one cell string, the trap transistor having a trap gate provided as a portion of the stack trap guard.

5. A method of fabricating a NAND flash memory device, the method comprising:

forming an isolation trench and forming an active region in a semiconductor substrate;

forming a facing bar on the semiconductor substrate in which the active region is subsequently formed;

stacking a subsidiary material layer and a mold layer in contact with a side surface of the facing bar;

removing the subsidiary material layer to form a mold;

depositing a gate material on the side surface of the facing bar on which the mold is formed; and

etching the gate material deposited on the side surface of the facing bar to form a gate electrode of a transistor,

wherein the facing bar is formed to extend in a horizontal direction with respect to a horizontal surface of the semiconductor substrate.

6. The method of claim 5, further comprising forming a capping layer on a region, from which the gate material is etched, to obtain an air gap.