THREE-DIMENSIONAL MEMORY DEVICE WITH THICKENED WORD LINES IN TERRACE REGION AND METHOD OF MAKING THEREOF

• US 20190148392A1
• Filed: 11/15/2017
• Published: 05/16/2019
• Est. Priority Date: 11/15/2017
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: KANNO, Yoshihiro, KANAKAMEDALA, Senaka Krishna, MAKALA, Raghuveer S., ZHANG, Yanli, LIU, Jin, CHOWDHURY, Murshed
• Granted Patent: US 10,453,854 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

Claims

1. A three-dimensional memory device comprising:

an alternating stack of insulating layers and electrically conductive layers comprising a doped semiconductor material located over a substrate, wherein the alternating stack includes a memory array region in which each of the electrically conductive layers is present and a terrace region in which the electrically conductive layers have a respective lateral extent that decreases as a function of a vertical distance from the substrate;

memory stack structures located in the memory array region and vertically extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and

contact via structures located in the terrace region and contacting a respective one of the electrically conductive layers,

wherein each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within the terrace region.

2. The three-dimensional memory device of claim 1, wherein each of the contact via structures contacts the contact portion of a respective one of the electrically conductive layers.

3. The three-dimensional memory device of claim 1, wherein each of the electrically conductive layers other than a topmost one of the electrically conductive layers has the respective first thickness throughout the memory array region and within a respective portion of the terrace region having an areal overlap with any overlying one of the electrically conductive layers in a plan view.

4. The three-dimensional memory device of claim 2, wherein, for each of the electrically conductive layers other than a topmost one of the electrically conductive layers, the portion having the respective second thickness does not have an areal overlap with any overlying one of the electrically conductive layers in the plan view.

5. The three-dimensional memory device of claim 1, wherein each of the electrically conductive layers comprises:

a first doped polycrystalline semiconductor material portion having a respective first thickness throughout; and

a second doped polycrystalline semiconductor material portion contacting a top surface of the first doped polycrystalline semiconductor material portion and a respective one of the contact via structures.

6. The three-dimensional memory device of claim 5, wherein the first doped polycrystalline semiconductor material portion and the second doped polycrystalline semiconductor material portion differ in composition.

7. The three-dimensional memory device of claim 5, wherein the second doped polycrystalline semiconductor material portion has a thickness that is a difference between the respective second thickness and the respective first thickness.

8. The three-dimensional memory device of claim 1, further comprising a retro-stepped dielectric material portion located in the terrace region and overlying the alternating stack and including a stepped bottom surface that contacts surfaces of the electrically conductive layers.

9. The three-dimensional memory device of claim 8, further comprising dielectric spacers located on sidewalls of a respective one of the insulating layers, and on a sidewall of one of the electrically conductive layers that overlies the respective one of the insulating layers, and contacting the retro-stepped dielectric material portion, wherein the insulating layers are laterally spaced from the retro-stepped dielectric material portion by the dielectric spacers.

10. The three-dimensional memory device of claim 9, wherein each of the electrically conductive layers contacts a top surface of a respective first one of the dielectric spacers and contacts a sidewall of a respective second one of the dielectric spacers.

11. The three-dimensional memory device of claim 1, wherein:

the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;

the substrate comprises a silicon substrate;

the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;

the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

12. A method of forming a three-dimensional memory device, comprising:

forming an alternating stack of insulating layers and semiconductor material layers over a substrate, wherein the alternating stack includes a memory array region in which each of the semiconductor material layers is present and a terrace region in which the semiconductor material layers have a respective lateral extent that decreases as a function of a vertical distance from the substrate;

forming self-aligned semiconductor material portions on physically exposed surfaces of the semiconductor material layers in the terrace region employing a selective semiconductor deposition process in which a semiconductor material grows from the physically exposed surfaces of the semiconductor material layers and does not grow from surfaces of the insulating layers;

forming a retro-stepped dielectric material portion including a stepped bottom surface on the self-aligned semiconductor material portions;

forming memory stack structures through the alternating stack in the memory array region, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and

forming contact via structures through the retro-stepped dielectric material portion.

13. The method of claim 12, wherein:

the semiconductor material layers comprise a first doped semiconductor material; and

the self-aligned semiconductor material portions comprise a second doped semiconductor material.

14. The method of claim 13, wherein the contact via structures are formed directly on the self-aligned semiconductor material portions.

15. The method of claim 12, further comprising:

forming lateral recesses by removing the semiconductor material layers and the self-aligned semiconductor material portions; and

forming electrically conductive layers in volumes of the lateral recesses by depositing at least one conductive material therein.

16. The method of claim 15, wherein the contact via structures are formed directly on the electrically conductive layers.

17. The method of claim 15, further comprising:

forming a backside trench through the alternating stack;

introducing an etchant into the backside trench, wherein the etchant etches the semiconductor material layers and the self-aligned semiconductor material portions selective materials of the insulating layers and the retro-stepped dielectric material portion; and

forming a backside blocking dielectric layer on physically exposed surfaces of the insulating layers, the retro-stepped dielectric material portion, and the memory stack structures inside the backside recesses, wherein the electrically conductive layers are formed on the backside blocking dielectric layer.

18. The method of claim 15, wherein each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within the terrace region

19. The method of claim 12, further comprising forming dielectric spacers on sidewalls of the insulating layers and the semiconductor material layers in the terrace region prior to forming the self-aligned semiconductor material portions, wherein the retro-stepped dielectric material portion is formed on sidewalls of the dielectric spacers.

20. The method of claim 18, wherein each of the self-aligned semiconductor material portions is formed directly on a top surface of a respective first one of the dielectric spacers and a sidewall of a respective second one of the dielectric spacers.