CURRENT BALANCING, CURRENT SENSOR, AND PHASE BALANCING APPARATUS AND METHOD FOR A VOLTAGE REGULATOR

• US 20190154739A1
• Filed: 01/22/2019
• Published: 05/23/2019
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: SCHROM, Gerhard, HODGSON, J. Keith, LYAKHOV, Alexander, TANG, Chiu Keung, RAGHURAMAN, Narayanan, NATARAJAN, Narayanan
• Granted Patent: US 10,641,799 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G06T 3/40 Scaling of whole images or parts thereof, e.g. expanding or contracting
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/1566 with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H03L 5/00 Automatic control of voltage, current, or power
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/685 the quantisation value generators of both converters being arranged in a common two-dimensional array

Abstract

Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

Claims

1. An apparatus comprising:

a first p-type transistor coupled to a power supply rail to provide an input power supply voltage and current, wherein the first p-type transistor is controlled by a first switchable signal;

a second p-type transistor coupled in series with the first p-type transistor, wherein the second p-type transistor is biased by a first bias;

a first n-type transistor coupled in series with the second p-type transistor, wherein the first n-type transistor is biased by a second bias;

a second n-type transistor coupled to series with the first n-type transistor, wherein the wherein the second p-type transistor is controlled by a second switchable signal, wherein the a second n-type transistor is coupled to ground;

a plurality of drivers to drive pulse width modulated (PWM) signals as the first and second switchable signals; and

a modulator to generate one or more PWM signals as input to the plurality of drivers.

2. The apparatus of claim 1, wherein the first and second biases are a function of the input power supply voltage.

3. The apparatus of claim 1 comprises:

a first current sensor to sense current through the first p-type transistor; and

a second current sensor to sense current through the first n-type transistor.

4. The apparatus of claim 3, wherein the first and second current sensors include a common gate amplifier.

5. The apparatus of claim 3, wherein the first current sensor comprises:

a third p-type transistor coupled to the input power supply rail, wherein a gate of the third p-type transistor is coupled to a drain of the first p-type transistor;

a fourth p-type transistor coupled in series with the third p-type transistor, wherein a gate of the fourth p-type transistor is controllable by the first switchable signal; and

a fifth p-type transistor coupled in series with the fourth p-type transistor, wherein a gate of the fifth p-type transistor is controllable by the first bias.

6. The apparatus of claim 5, comprises first and second current mirrors, wherein the first current sensor comprises:

a sixth p-type transistor coupled to the input power supply rail, wherein a gate of the sixth p-type transistor is coupled to a drain of the first p-type transistor, wherein drain terminals of the third and sixth p-type transistors are coupled to the first and second current mirrors.

7. The apparatus of claim 6 comprises:

seventh p-type transistor coupled in series with the sixth p-type transistor, wherein a gate of the seventh p-type transistor is controllable by the first switchable signal; and

an eighth p-type transistor coupled in series with the seventh p-type transistor, wherein a gate of the eighth p-type transistor is controllable by the first bias, wherein the eighth p-type transistor is coupled to the power supply rail.

8. The apparatus of claim 5, wherein the second current sensor comprises:

a third n-type transistor coupled in series with the fifth p-type transistor, wherein a gate of the third n-type transistor is controllable by the second bias;

a fourth n-type transistor coupled in series with the third n-type transistor, wherein a gate of the fourth n-type transistor is controllable by the second switchable signal; and

a fifth n-type transistor coupled in series with the fourth n-type transistor, wherein a gate of the fifth p-type transistor is controllable by a source of the first n-type transistor.

9. The apparatus of claim 8, comprises third and fourth current mirrors, wherein the second current sensor comprises:

a sixth n-type transistor coupled to ground, wherein a gate of the sixth n-type transistor is coupled to the second bias.

10. The apparatus of claim 9 comprises:

seventh n-type transistor coupled in series with the sixth n-type transistor, wherein the a gate of the seventh n-type transistor is controllable by the second switchable signal; and

an eighth n-type transistor coupled in series with the seventh n-type transistor, wherein a gate of the eighth n-type transistor is controllable by the source of the first n-type transistor, wherein the eighth n-type transistor is coupled to ground, and wherein drain terminals of the seventh and eighth n-type transistors are coupled to the third and fourth current mirrors.

11. An apparatus comprising:

a first current sensor coupled to an input power supply rail and to a high-side switch of a DC-DC converter;

a second current sensor coupled to ground and to a low-side switch of the DC-DC converter, wherein the high-side switch is coupled in series with the low-side switch;

an n-type transistor coupled in series with the first current sensor; and

a p-type transistor coupled in series with the n-type transistor and the second current sensor.

12. The apparatus of claim 11, wherein the n-type transistor is a first n-type transistor, wherein the apparatus comprises a second n-type transistor, and wherein a gate of the first n-type transistor is coupled to a gate of the second n-type transistor.

13. The apparatus of claim 12, wherein the p-type transistor is a first p-type transistor, wherein the apparatus comprises a second p-type transistor, wherein a gate of the first p-type transistor is coupled to a gate of the second p-type transistor.

14. The apparatus of claim 13, wherein the second p-type transistor and the second n-type transistor are coupled in series.

15. The apparatus of claim 13 comprises a unity gain amplifier coupled to the second n-type transistor and the second p-type transistor.

16. The apparatus of claim 12, wherein the second n-type transistor is coupled to a current mirror.

17. A system comprising:

a processor core;

a DC-DC converter to provide a regulated power supply to the processor core, wherein the DC-DC converter comprises;

a first current sensor coupled to an input power supply rail and to a high-side switch of a DC-DC converter;

a second current sensor coupled to ground and to a low-side switch of the DC-DC converter, wherein the high-side switch is coupled in series with the low-side switch;

an n-type transistor coupled in series with the first current sensor; and

a p-type transistor coupled in series with the n-type transistor and the second current sensor; and

an inductor coupled to the high-side and low-side switches of the DC-DC converter;

a capacitor coupled to the inductor, wherein the inductor is coupled to the processor core; and

a wireless interface to allow the processor core to communicate with another device.

18. The system of claim 17, wherein the n-type transistor is a first n-type transistor, wherein the apparatus comprises a second n-type transistor, and wherein a gate of the first n-type transistor is coupled to a gate of the second n-type transistor.

19. The system of claim 18, wherein the p-type transistor is a first p-type transistor, wherein the apparatus comprises a second p-type transistor, wherein a gate of the first p-type transistor is coupled to a gate of the second p-type transistor, wherein the second p-type transistor and the second n-type transistor are coupled together in series.

20. The system of claim 19 comprises a unity gain amplifier coupled to the second n-type transistor and the second p-type transistor, wherein the second n-type transistor is coupled to a current mirror.