MIXED CROSS POINT MEMORY
4 Assignments
0 Petitions
Accused Products
Abstract
Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.
12 Citations
21 Claims
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1. (canceled)
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2. A memory device, comprising:
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a first plurality of pillars arranged in a three-dimensional cross point architecture with a first access line and a second access line, wherein at least one pillar of the first plurality comprises a first memory storage element coupled to the first access line and the second access line; and a second plurality of pillars arranged in a three-dimensional cross point architecture with a third access line, wherein at least one pillar of the second plurality comprises; a second memory storage element coupled to the third access line; and a selector device coupled to the second memory storage element and the second access line or a fourth access line. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus, comprising:
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a pillar comprising a first portion and a second portion, wherein; the first portion comprises a self-selecting memory storage element; the second portion comprises a memory storage element and a selector device; and an access line coupled with the first portion and the second portion. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. An apparatus, comprising:
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a pillar comprising; a first portion coupled with a first access line and a second access line, and a second portion coupled with the second access line and a third access line, wherein the first portion comprises a self-selecting memory storage element and the second portion comprises a memory storage element and a selector device; and a memory controller coupled with the pillar, the memory controller configured to; write a first logic value to the self-selecting memory storage element based at least in part on applying a first voltage between the first access line and the second access line; and write a second logic value to the memory storage element based at least in part on applying a second voltage between the second access line and the third access line. - View Dependent Claims (19, 20, 21)
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Specification