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MEMORY DEVICES WITH DISTRIBUTED BLOCK SELECT FOR A VERTICAL STRING DRIVER TILE ARCHITECTURE

  • US 20190156893A1
  • Filed: 11/17/2017
  • Published: 05/23/2019
  • Est. Priority Date: 11/17/2017
  • Status: Active Grant
First Claim
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1. A memory device having a tile architecture, the memory device comprising:

  • a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry, at least one portion of the distributed block select circuit within a first pair of tiles of the multiple pairs of tiles physically offset from at least one other portion of the distributed block select circuit within second pair of tiles of the multiple pairs of tiles.

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