MEMORY DEVICES WITH DISTRIBUTED BLOCK SELECT FOR A VERTICAL STRING DRIVER TILE ARCHITECTURE

• US 20190156893A1
• Filed: 11/17/2017
• Published: 05/23/2019
• Est. Priority Date: 11/17/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Eric N.
• Granted Patent: US 10,453,533 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Memory device having a tile architecture are disclosed. The memory device may include a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry. Another memory device may include a memory array, and a CMOS under array region. At least some tile regions may include portions of a total amount of block select circuitry distributed throughout the CUA region, vertical string drivers located outside of the memory array, and page buffer circuitry coupled with the memory array. Another memory device may include a first tile pair including a first tile, a second tile, a first vertical string driver therebetween, a first page buffer region that is greater than 50% of area for the first tile pair, and a first portion of a distributed block select circuitry.

Claims

1. A memory device having a tile architecture, the memory device comprising:

a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry, at least one portion of the distributed block select circuit within a first pair of tiles of the multiple pairs of tiles physically offset from at least one other portion of the distributed block select circuit within second pair of tiles of the multiple pairs of tiles.

2. The memory device of claim 1, wherein the block select circuit is distributed across all tiles in the first plane.

3. The memory device of claim 2, wherein the block select circuit is distributed evenly across all tiles in the first plane.

4. The memory device of claim 2, wherein the block select circuit is distributed unevenly across the tiles in the first plane.

5. The memory device of claim 1, wherein the block select circuit is distributed across only a subset of the tiles in the first plane.

6. The memory device of claim 1, further comprising a second plane having multiple pairs of tiles.

7. The memory device of claim 1, further comprising a CMOS under array region including the first plane.

8. The memory device of claim 7, further comprising a memory array coupled with the CMOS under array region.

9. The memory device of claim 8, wherein the memory array is a three-dimensional memory array.

10. A memory device having a tile architecture, the memory device comprising:

a first tile pair including a first tile, a second tile, a first vertical string driver positioned between the first tile and the second tile, and a first page buffer region that is greater than 50% of area for the first tile pair, the first tile including a first portion of a distributed block select circuitry and the second tile including a second portion of the distributed block select circuitry; and

a second tile pair including a third tile, a fourth tile, a second vertical string driver positioned between the third tile and the fourth tile, a second page buffer region that is greater than 50% of area for the second tile pair, the third tile including a third portion of the distributed block select circuitry and the fourth tile including a fourth portion of the distributed block select circuitry,

wherein the first portion, the second portion, the third portion, and the fourth portion of the distributed block select circuitry are each coupled to the first vertical string driver and the second vertical string driver.

11. The memory device of claim 10, further comprising a memory array coupled to the first and second page buffer regions and the distributed block select circuitry.

12. The memory device of claim 11, wherein the first tile pair and the second tile pair each include a space adjacent to the respective distributed block select circuitry that includes peripheral circuitry for the memory array.

13. The memory device of claim 11, further comprising additional tile pairs.

14. The memory device of claim 13, wherein at least some of the additional tile pairs include portions of the distributed block select circuitry.

15. The memory device of claim 14, wherein all of the additional tile pairs include portions of the distributed block select circuitry.

16. The memory device of claim 14, wherein at least some of the additional tile pairs do not include any portions of the distributed block select circuitry.

17. The memory device of claim 16, wherein the additional tile pairs that do not include any portions of the distributed block select circuitry include additional page buffer regions.

18. The memory device of claim 17, wherein the additional page buffer regions are greater than 50% of the area for their respective tile groups.

19. The memory device of claim 17, wherein at least some adjacent tile groups include peripheral circuit areas that are contiguous.

20. A memory device having a tile architecture, comprising:

a memory array; and

a CMOS under array (CUA) region including;

at least some tile regions including portions of a total amount of block select circuitry distributed throughout the CUA region, each portion of the portions of the block select circuitry offset from at least one other portion of the portions of the block select circuitry;

vertical string drivers located outside of the memory array, search vertical string driver of the vertical string drivers coupled to each portion of the block select circuitry located within different tile regions; and

page buffer circuitry coupled with the memory array.

21. The memory device of claim 20, wherein the block select circuitry is distributed throughout the tile regions of the CUA region in equal portions.

22. The memory device of claim 20, wherein at least some tile regions include page buffer circuitry.

23. The memory device of claim 22, wherein an area of the page buffer circuitry is greater than 50% of at least some of the tile regions.

24. The memory device of claim 20, wherein the CUA region includes peripheral circuits located within an open area of at least some of the tile regions.

25. The memory device of claim 24, wherein the open area with the peripheral circuits is contiguous between one or more adjacent tile regions.