Address/Command Chip Synchronized Autonomous Data Chip Address Sequencer for A Distributed Buffer Memory System
First Claim
1. A memory system for storing data in response to commands received from a Host, the memory system comprising:
- a memory control circuit to receive commands from the Host and to output module command and control signals;
at least one memory device configured to store data and receive command signals from the memory control circuit;
at least one data buffer circuit associated with the at least one memory device;
a communications link for communicating data between the Host and the at least one data buffer circuit; and
a control communications link between the memory control circuit and the at least one data buffer circuit,wherein the memory control circuit is configured to;
in response to receiving a store command and store data tag from the Host, obtain a local store data tag from a memory control circuit local address sequencer;
associate the Host store data tag with the memory control circuit store data tag; and
store the relationship in a mapping table in the memory control circuit.
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Accused Products
Abstract
One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.
14 Citations
25 Claims
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1. A memory system for storing data in response to commands received from a Host, the memory system comprising:
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a memory control circuit to receive commands from the Host and to output module command and control signals; at least one memory device configured to store data and receive command signals from the memory control circuit; at least one data buffer circuit associated with the at least one memory device; a communications link for communicating data between the Host and the at least one data buffer circuit; and a control communications link between the memory control circuit and the at least one data buffer circuit, wherein the memory control circuit is configured to; in response to receiving a store command and store data tag from the Host, obtain a local store data tag from a memory control circuit local address sequencer; associate the Host store data tag with the memory control circuit store data tag; and store the relationship in a mapping table in the memory control circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A memory system for reading and writing data to a memory device, the system comprising:
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at least one memory control circuit to receive commands from a Host and to output command and control signals, the memory control circuit having a local address sequencer that has local store tag locations in a sequence; at least one memory device configured to read and store data, and receive command signals from the memory control circuit; at least one data buffer circuit associated with the at least one memory control circuit, the data buffer circuit having a local address sequencer which has local store tag locations in the same sequence as the local address sequencer of the at least one memory control circuit; a data communications link for communicating data between the Host and the at least one data buffer circuit; and a control communications link between the at least one memory control circuit, the at least one memory device and the at least one data buffer circuit for transmitting reading and writing operation signals of the memory system; wherein the at least one memory control circuit is configured to; process a store command into a write-to-buffer command and a store-from-buffer command; obtain a local store data tag from a local address sequencer of the at least one memory control circuit upon receiving a store command; send the write-to-buffer command to the at least one data buffer circuit; send the store command to the at least one memory device; and send the store-from-buffer command along with store data tag to the at least one data buffer circuit, and wherein the at least one data buffer circuit is configured to; obtain a local store data tag from a local address sequencer of the at least one data buffer circuit upon receiving the write-to-buffer command; send incoming store data into data buffer pointed to by the local store data tag obtained by the local address sequencer of the at least one data buffer circuit; pull out store data from the local data buffer pointed to by store data tag received from the at least one memory control circuit, and send store data to the at least one memory device.
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14. A method for storing data in memory devices, the method comprising:
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obtaining a local store data tag from an address sequencer in a memory control circuit upon receiving a host store command; associating a host tag to the memory control circuit local store data tag and storing the associated tags in a mapping table; processing the store command in the memory control circuit into a write-to-buffer command and a store-from-buffer command; sending the write-to-buffer command to a data buffer circuit; obtaining a local store data tag from an address sequencer in a data buffer circuit; and pushing incoming data into the location in the data buffer circuit pointed to by the local store data tag obtained from the data buffer circuit local address sequencer. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A method of checking local address sequencers in a distributed memory system having a remote memory control circuit, the method comprising:
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pulling a next to be used store data tag from each local address sequencer of a plurality of data buffer circuits; comparing the store data tags recovered from the local address sequencer of each data buffer circuit; and if any of the tags from the data buffer circuits are different, issuing a recovery command. - View Dependent Claims (21, 22)
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23. A method of checking the local address sequencers in a memory system having a remote memory control circuit, the method comprising:
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sending the next tag to be issued from a local address sequencer of the memory control circuit to a data buffer circuit; comparing the next tag to be issued from a local address sequencer of the data buffer circuit against the next to be used tag sent by the memory control circuit; and if the tags do not match, issuing a recovery command. - View Dependent Claims (24, 25)
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Specification