SEMICONDUCTOR MEMORY

• US 20190163398A1
• Filed: 08/30/2018
• Published: 05/30/2019
• Est. Priority Date: 11/30/2017
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: TOKIWA, Naoya
• Granted Patent: US 10,642,537 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits

Abstract

A semiconductor memory includes a first plane that includes a first memory cell array, a second plane that includes a second memory cell array, and a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane and a second circuit configured to store a second priority for a second operation performed on the second plane, and is configured to control the first and second operations based on the first priority and the second priority. When a value of the second priority is higher than a value of the first priority, the control circuit controls the first operation such that a timing of a process executed in the first operation does not overlap with a timing of a process executed in the second operation.

Claims

1. A semiconductor memory comprising:

a first plane that includes a first memory cell array;

a second plane that includes a second memory cell array; and

a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane and a second circuit configured to store a second priority for a second operation performed on the second plane, and is configured to control the first and second operations based on the first priority and the second priority,

wherein when a value of the second priority is higher than a value of the first priority, the control circuit controls the first operation such that a timing of a process executed in the first operation does not overlap with a timing of a process executed in the second operation.

2. The semiconductor memory according to claim 1,

wherein the control circuit further includes a first sequencer circuit for the first plane and a second sequencer circuit for the second plane,

the second sequencer outputs a first signal that indicates a start of the second process, and

the first sequencer controls a start timing of the first process based on the first signal.

3. The semiconductor memory according to claim 2,

wherein the first sequencer delays the start timing of the first process.

4. The semiconductor memory according to claim 2,

wherein the first signal is output based on an amount of current consumption caused by the second process.

5. The semiconductor memory according to claim 1,

wherein the first and second circuits set values of the first and second priorities based on a command for the first and second operations to be performed on the first and second planes, an address indicating a selected area in the first and second planes, and a second signal indicating an operating status of each of the first and second planes.

6. The semiconductor memory according to claim 1,

wherein the control circuit receives from a controller, a first command that includes an instruction to change a priority of the first operation along with a command for the first operation, and

the control circuit sets a value of the first priority based on the first command.

7. The semiconductor memory according to claim 1,

wherein the control circuit receives from a controller, a command that includes an instruction to transmit a value of the first priority of the first operation, and

the control circuit transmits the value of the first priority to the controller in response to the command.

8. A memory system comprising:

a controller; and

a semiconductor memory including a first plane of memory cells, a second plane of memory cells, and a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane in response to a first command from the controller and a second circuit configured to store a second priority for a second operation performed on the second plane in response to a second command from the controller, wherein

the controller is configured to control the first and second operations based on the first priority and the second priority, such that when a value of the second priority is higher than a value of the first priority, the control circuit controls the first operation such that a timing of a process executed in the first operation does not overlap with a timing of a process executed in the second operation.

9. The memory system according to claim 8,

wherein the control circuit further includes a first sequencer circuit for the first plane and a second sequencer circuit for the second plane,

the second sequencer outputs a first signal that indicates a start of the second process, and

the first sequencer controls a start timing of the first process based on the first signal.

10. The memory system according to claim 9,

wherein the first sequencer delays the start timing of the first process.

11. The memory system according to claim 9,

wherein the first signal is output based on an amount of current consumption caused by the second process.

12. The memory system according to claim 8,

wherein the first and second circuits set values of the first and second priorities based on the first and second commands, an address indicating a selected area in the first and second planes, and a second signal indicating an operating status of each of the first and second planes.

13. The memory system according to claim 8,

wherein the control circuit receives from the controller, a third command that includes an instruction to change a priority of the first operation along with the first command, and

the control circuit sets a value of the first priority based on the third command.

14. The memory system according to claim 8,

wherein the control circuit receives from the controller, a third command that includes an instruction to transmit a value of the first priority of the first operation, and

the control circuit transmits the value of the first priority to the controller in response to the third command.

15. A method of performing parallel operations in a semiconductor memory including a first plane of memory cells, a second plane of memory cells, and a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane and a second circuit configured to store a second priority for a second operation performed on the second plane, said method comprising:

controlling the first and second operations based on the first priority and the second priority, such that when a value of the second priority is higher than a value of the first priority, adjusting a timing of a process executed in the first operation so as to not overlap with a timing of a process executed in the second operation.

16. The method according to claim 15, further comprising:

determining that an amount of current consumption by the overlapping processes in the first and second operations exceeds a threshold; and

delaying the process executed in the first operation so as to not overlap with the timing of the process executed in the second operation.

17. The method according to claim 15, further comprising:

setting values of the first and second priorities based on a command for the first and second operations to be performed on the first and second planes, respectively, an address indicating a selected area in the first and second planes, and a second signal indicating an operating status of each of the first and second planes.

18. The method according to claim 15, further comprising:

setting a value of the first priority based a first command that includes an instruction to change a priority of the first operation along with a command for the first operation.

19. The method according to claim 15, further comprising:

receiving a command that includes an instruction to return a value of the first priority of the first operation, and

returning the value of the first priority in response to the command.

20. The method according to claim 15, further comprising:

increasing a value of the first priority after the second operation completes.