Residue-Free Metal Gate Cutting For Fin-Like Field Effect Transistor

• US 20190164839A1
• Filed: 03/28/2018
• Published: 05/30/2019
• Est. Priority Date: 11/30/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Ya-Yi, Hsiao, Yi-Hsuan, Ku, Shu-Yuan, Chen, Ryan Chia-Jen, Chang, Ming-Ching
• Granted Patent: US 10,460,994 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

Claims

1. A method comprising:

receiving an integrated circuit (IC) device structure that includes;

a substrate;

one or more fins disposed over the substrate;

a plurality of gate structures disposed over the one or more fins, wherein the plurality of gate structures traverses the one or more fins and includes first and second gate structures;

a dielectric layer disposed between and adjacent to the plurality of gate structures; and

a patterning layer disposed over the plurality of gate structures and the dielectric layer;

creating an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer between and adjacent to the first and second gate structures; and

removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

2. The method of claim 1, wherein the removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer comprises performing an anisotropic etching process.

3. The method of claim 2, wherein the anisotropic etching process uses an etchant with an etch selectivity of about 1:

1 between the dielectric layer, the first gate structure, and the second gate structure.

4. The method of claim 2, wherein the anisotropic etching process includes a plurality of etching cycles for removing, in thickness increments, the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

5. The method of claim 4, wherein each of the plurality of etching cycles in the anisotropic etching process comprises:

depositing an etch protection layer on a bottom surface and sidewall surfaces of the IC device structure defining the opening; and

etching the etch protection layer on the bottom surface as well as an incremental thickness of the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer for a time period,

wherein the time period is controlled so as to avoid penetrating through the etch protection layer on the sidewall surfaces.

6. The method of claim 5, wherein the etch protection layer is further deposited over a top surface of the patterning layer in each etching cycle, and wherein the etch protection layer and an incremental thickness of the patterning layer are subsequently removed in each etching cycle.

7. The method of claim 1, wherein the patterning layer includes a barrier layer and a hard mask layer, wherein the barrier layer is disposed over the plurality of gate structures and the dielectric layer, and the hard mask layer is disposed over the barrier layer, and wherein creating the opening comprises etching through the hard mask layer and the barrier layer to expose the portion of the first gate structure, the portion of the second gate structure, and the portion of the dielectric layer.

8. The method of claim 1, wherein the removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the first dielectric layer penetrates partially through an isolation feature disposed on the substrate.

9. The method of claim 1, wherein the dielectric layer is a first dielectric layer, wherein the removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer extends the opening, the method further comprising filling the extended opening with a second dielectric layer.

10. The method of claim 1, wherein the one or more fins include first and second fins extending along a first direction, wherein the opening exposes in the first direction the portions of the first and second gate structures but does not expose any other of the plurality of gate structures, wherein the plurality of gate structures extends along a second direction that is substantially perpendicular to the first direction, wherein the opening extends in the second direction between the first and second fins, and wherein the opening does not expose the first or second fin.

11. A method comprising:

forming a plurality of fins over a substrate and extending along a first direction;

forming an inter-layer dielectric (ILD) layer over the plurality of fins;

forming a first metal gate structure and a second metal gate structure over the plurality of fins and extending along a second direction that is substantially perpendicular to the first direction;

forming a patterning layer over the first and second metal gate structures and the ILD layer;

defining a cut window in the patterning layer for cutting the first and second metal gate structures, wherein the cut window exposes a portion of the first metal gate structure, a portion of the second metal gate structure, and a portion of the ILD layer between and adjacent to the first and second metal gate structures; and

simultaneously etching the exposed portion of the first metal gate structure, the exposed portion of the second metal gate structure, and the exposed portion of the ILD layer.

12. The method of claim 11, wherein the first and second metal gate structures are formed by replacing dummy gate structures, wherein the first and second metal gate structures include metal gates and spacers disposed on sidewall surfaces of the metal gates, wherein simultaneously etching the exposed portion of the first metal gate structure and the exposed portion of the second metal gate structure comprises simultaneously etching the metal gates and the spacers.

13. The method of claim 11, wherein the simultaneously etching comprises performing a dry etching process, and wherein the dry etching process uses an etchant configured to etch the ILD layer and the first and second metal gate structures at a substantially same etch rate.

14. The method of claim 13, wherein the dry etching process includes a plurality of etching cycles for simultaneously etching, in thickness increments, the exposed portion of the first metal gate structure, the exposed portion of the second metal gate structure, and the exposed portion of the ILD layer.

15. The method of claim 14, wherein each of the plurality of etching cycles in the dry etching process comprises:

depositing an etch protection layer on a bottom surface and sidewall surfaces defining the cut window; and

etching the etch protection layer on the bottom surface and an incremental thickness of the exposed portion of the first metal gate structure, the exposed portion of the second metal gate structure, and the exposed portion of the ILD layer for a time period,

wherein the time period is controlled so as to avoid penetrating through the etch protection layer on the sidewall surfaces.

16. The method of claim 11, wherein the patterning layer includes a titanium nitride layer and a silicon nitride layer, wherein the titanium nitride layer is disposed over the first and second metal gate structures and the ILD layer, and the silicon nitride layer is disposed over the titanium nitride layer, and wherein defining the cut window comprises etching through the silicon nitride layer and the titanium nitride layer to expose the portion of the first metal gate structure, the portion of the second metal gate structure, and the portion of the ILD layer.

17. The method of claim 11, wherein the ILD layer is a first ILD layer, wherein simultaneously etching the exposed portion of the first metal gate structure, the exposed portion of the second metal gate structure, and the exposed portion of the ILD layer extends the cut window, the method further comprising filling the extended cut window with a second ILD layer.

18. The method of claim 11, wherein the plurality of fins include first and second fins extending along the first direction, wherein the cut window exposes in the first direction the portions of the first and second metal gate structures but does not expose any other metal gate structure, wherein the cut window extends in the second direction between the first and second fins but does not expose the first or second fin.

19. An integrated circuit (IC) device comprising:

a substrate;

a first fin and a second fin disposed over the substrate and extending along a first direction;

a first metal gate structure and a second metal gate structure disposed over the first and second fins and extending along a second direction that is substantially perpendicular to the first direction, wherein, for a portion of a distance between the first and second fins in the second direction, a distance between the first and second metal gate structures in the first direction is dividable into three contiguous sections including a first section, a second section, and a third section;

a first inter-layer dielectric (ILD) layer disposed in the first and third sections; and

a second ILD layer disposed in the second section such that the second section does not contain any portion of the first ILD layer, any portion of the first metal gate structure, or any portion of the second metal gate structure.

20. The IC device of claim 19, further comprising:

an isolation feature disposed over the substrate and adjacent to the first and second fins, wherein the second ILD layer extends through an upper portion of the isolation feature.