Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle

• US 20190164974A1
• Filed: 01/08/2019
• Published: 05/30/2019
• Est. Priority Date: 08/05/2008
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 10,644,002 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state.

Claims

1-21. -21. (canceled)

22. A semiconductor memory cell comprising:

a first silicon controlled rectifier device having a first region, a first floating body region, a first buried layer region, and a first substrate region;

a second silicon controlled rectifier device having a second region, a second floating body region, a second buried layer region, and a second substrate region;

a transistor comprising said first region, said first floating body region, said second region, and a gate;

wherein said first floating body region is common to said second floating body region;

wherein said first buried layer region is common to said second buried layer region;

wherein said first substrate region is common to said second substrate region;

wherein said transistor is usable to access said memory cell; and

wherein a state of said memory cell is maintained through a positive voltage applied to said first and second substrate regions.

23. The memory cell of claim 22, wherein said first floating body region and said second floating body region have a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

wherein said first region and said second region have a second conductivity type selected from said p-type conductivity type and said n-type conductivity type, said second conductivity type being different from said first conductivity type;

wherein said first buried layer region and said second buried layer region have said second conductivity type; and

wherein said first substrate region and said second substrate region have said first conductivity type.

24. The memory cell of claim 22, wherein said first and second floating body regions comprise side surfaces, said memory cell further comprising insulating layers bounding said side surfaces.

25. The memory cell of claim 22, wherein said positive voltage applied to said first and second substrate regions is a constant positive voltage bias.

26. The memory cell of claim 22, wherein said positive voltage applied to said first and second substrate regions is a periodic pulse of positive voltage.

27. The memory cell of claim 22, wherein said state of said memory cell is stored in said first floating body region and said second floating body region.

28. The memory cell of claim 27, wherein a maximum potential that can be stored in said first and second floating body regions is increased by said applying a voltage to said first and second substrate regions, resulting in a relatively larger memory window.

29. The memory cell of claim 22, wherein said first and second floating body regions and said first and second regions are formed in a fin that extends above said first and second buried layer regions, and said first and second floating body regions are between said first and second regions.

30. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each semiconductor memory cell comprises;

a first silicon controlled rectifier device having a first region, a first floating body region, a first buried layer region, and a first substrate region;

a second silicon controlled rectifier device having a second region, a second floating body region, a second buried layer region, and a second substrate region;

a transistor comprising said first region, said first floating body region, said second region, and a gate;

wherein said first floating body region is common to said second floating body region;

wherein said first buried layer region is common to said second buried layer region;

wherein said first substrate region is common to said second substrate region;

wherein a state of said memory cell is maintained through a positive voltage applied to said first and second substrate regions;

wherein said transistor is usable to access said memory cell;

wherein said first and second buried layer regions are commonly connected to at least two of said memory cells; and

wherein said first and second substrate regions are commonly connected to said at least two of said memory cells.

31. The semiconductor memory array of claim 30, wherein said first and second substrate regions are commonly connected to all of said cells in said array.

32. The semiconductor memory array of claim 30, wherein said first and second substrate regions are segmented to allow independent control of bias applied on a selected portion of said memory array.

33. The semiconductor memory array of claim 30, wherein said voltage applied to said first and second substrate regions is a constant positive voltage bias.

34. The semiconductor memory array of claim 30, wherein said voltage applied to said first and second substrate regions is a periodic pulse of positive voltage bias.

35. The semiconductor memory array of claim 30, wherein said state of said memory cell is stored in said first and second floating body regions.

36. The semiconductor memory array of claim 30, wherein said first and second floating body regions and said first and second regions are formed in a fin that extends above said first and second buried layer regions, and said floating body regions are between said first and second regions.

37. An integrated circuit comprising:

a semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises;

a first silicon controlled rectifier device having a first region, a first floating body region, a first buried layer region, and a first substrate region;

a second silicon controlled rectifier device having a second region, a second floating body region, a second buried layer region, and a second substrate region;

a transistor comprising said first region, said first floating body region, said second region, and a gate; and

a control circuit configured to provide electrical signals to said first and second substrate regions;

wherein said first floating body region is common to said second floating body region;

wherein said first buried layer region is common to said second buried layer region;

wherein said first substrate region is common to said second substrate region;

wherein a state of said memory cell is maintained through a positive voltage applied to said first and second substrate regions;

wherein said transistor is usable to access said memory cell;

wherein said first and second buried layer regions are commonly connected to at least two of said memory cells; and

wherein said first and second substrate regions are commonly connected to said at least two of said memory cells.

38. The integrated circuit of claim 37, wherein said first and second substrate regions are commonly connected to all of said cells in said array.

39. The integrated circuit of claim 37, wherein said first and second substrate regions are segmented to allow independent control of bias applied on a selected portion of said memory array.

40. The integrated circuit of claim 37, wherein said voltage applied to said first and second substrate regions is one of a constant positive voltage bias or a periodic pulse of positive voltage bias.

41. The integrated circuit of claim 37, wherein said first and second floating body regions and said first and second regions are formed in a fin that extends above said first and second buried layer regions, and said first and second floating body regions are between said first and second regions.