FULL RANGE REALIGNMENT RING OSCILLATOR

• US 20190165769A1
• Filed: 11/30/2017
• Published: 05/30/2019
• Est. Priority Date: 11/30/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TSAI, Tsung-Hsien, Hsieh, Chen-Hsiang, SHEEN, Ruey-Bin, CHANG, Chih-Hsien
• Granted Patent: US 10,461,723 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03K 3/356034 the input circuit having a differential configuration
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate. A drain of the P-type metal-oxide-semiconductor transistor and a drain of the N-type metal-oxide-semiconductor transistor are electrically connected to each other and are further electrically connected to a second input of the OR gate and a second input of the AND gate.

Claims

1. A realignment ring-cell circuit, comprising:

a single-to-differential unit having an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output;

an OR gate, wherein the first output for outputting is a first input to the OR gate;

an AND gate, wherein the second output for outputting is a first input to the AND gate;

a first P-type metal-oxide-semiconductor transistor, wherein a gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate; and

a first N-type metal-oxide-semiconductor transistor, wherein a gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate, wherein a drain of the P-type metal-oxide-semiconductor transistor and a drain of the N-type metal-oxide-semiconductor transistor are electrically connected to each other and are further electrically connected to a second input of the OR gate and a second input of the AND gate.

2. The realignment ring-cell circuit of claim 1, wherein a source of the P-type metal-oxide-semiconductor transistor is grounded and a source of the N-type metal-oxide-semiconductor transistor is grounded.

3. The realignment ring-cell circuit of claim 1, further comprises a second P-type metal-oxide-semiconductor transistor and a second N-type metal-oxide-semiconductor transistor, wherein the drain of the second P-type metal-oxide-semiconductor transistor and the drain of the second N-type metal-oxide-semiconductor transistor are electrically connected, and are further electrically connected to the drains of both P-type metal-oxide-semiconductor transistor and N-type metal-oxide-semiconductor transistor, wherein the gate of the second P-type metal-oxide-semiconductor transistor and the gate of the second N-type metal-oxide-semiconductor transistor are electrically connected, wherein the source of the second P-type metal-oxide-semiconductor transistor is grounded, wherein the source of the second N-type metal-oxide-semiconductor transistor is grounded.

4. The realignment ring-cell circuit of claim 1, wherein the single-to-differential unit further comprises an even-stage inverter train, an odd-stage inverter train, and a crossing letch.

5. The realignment ring-cell circuit of claim 4, wherein the even-stage inverter train further comprises an even number of serially connected inverters, and the odd-stage inverter train further comprises an odd number of serially connected inverters.

6. The realignment ring-cell circuit of claim 5, wherein the crossing latch further comprises two anti-parallel inverters.

7. The realignment ring-cell circuit of claim 6, wherein the even number is four, and the odd number is three.

8. The realignment ring-cell circuit of claim 7, wherein an input of the first inverter in the even-stage inverter train is electrically connected to an input of the first inverter in the odd-stage inverter train.

9. The realignment ring-cell circuit of claim 8, wherein an output of the last inverter in the even-stage inverter train is electrically connected to a first side of the crossing latch, wherein an output of the last inverter in the odd-stage inverter train is electrically connected to a second side of the crossing latch.

10. A full-range realignment ring oscillator circuit, comprising:

a full range realignment ring cell configured to realign a pulse signal with a realignment pulse, wherein the full range realignment ring cell has a first input and a second input; and

an even number of serially connected ring cells, wherein an output of the full range realignment ring cell is electrically connected to an input of a first ring cell in the even number of serially connected ring cells, wherein an output of a last ring cell in the even number of serially connected ring cells is electrically connected to the first input of the full range realignment ring cell.

11. The full-range realignment ring oscillator circuit of claim 10, wherein each of the ring cells in the even number of serially connected ring cells is an inverter.

12. The full-range realignment ring oscillator circuit of claim 10, wherein the second input of the full range realignment ring is electrically connected to a pulse generator.

13. The full-range realignment ring oscillator circuit of claim 10, wherein the full range realignment ring cell further comprises:

a single-to-differential unit having an input configured to receive a realignment signal, a first output for outputting and a second output for outputting;

an OR gate, wherein the first output of the single-to-differential unit is a first input to the OR gate;

an AND gate, wherein the second output of the single-to-differential unit is a first input to the AND gate;

a first P-type metal-oxide-semiconductor transistor, wherein the gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate; and

a first N-type metal-oxide-semiconductor transistor, wherein the gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate, wherein the drain of the P-type metal-oxide-semiconductor transistor and the drain of the N-type metal-oxide-semiconductor transistor are electrically connected and are further electrically connected to a second input of the OR gate and a second input of the AND gate.

14. The full-range realignment ring oscillator circuit of claim 13, wherein the full range realignment ring cell further comprises a second P-type metal-oxide-semiconductor transistor and a second N-type metal-oxide-semiconductor transistor, wherein the drain of the second P-type metal-oxide-semiconductor transistor and the drain of the second N-type metal-oxide-semiconductor transistor are electrically connected, and are further electrically connected to the drains of both P-type metal-oxide-semiconductor transistor and N-type metal-oxide-semiconductor transistor, wherein the gate of the second P-type metal-oxide-semiconductor transistor and the gate of the second N-type metal-oxide-semiconductor transistor are electrically connected, wherein the source of the second P-type metal-oxide-semiconductor transistor is grounded, wherein the source of the second N-type metal-oxide-semiconductor transistor is grounded.

15. The full-range realignment ring oscillator circuit of claim 13, wherein the sing-to-differential unit further comprises an even-stage inverter train, an odd-stage inverter train, and a crossing letch.

16. A method for operating a full range realignment ring oscillator, the method comprises:

deploying a full range realignment cell configured to realign a pulse signal with a realignment pulse comprising a single-to-differential unit, an OR gate, an AND gate, a P-type metal-oxide-semiconductor transistor and an N-type metal-oxide-semiconductor transistor;

converting a single-ended realignment signal to a first output for outputting a first differential output and a second output for outputting a second differential output; and

detecting a level of common drain to decide whether to turn on the P-type metal-oxide-semiconductor transistor or the N-type metal-oxide-semiconductor transistor.

17. The method of claim 16, further comprising when the common drain level is high, disabling the OR gate to block the first differential output signal.

18. The method of claim 17, further comprising pulling the output of the OR gate to high.

19. The method of claim 18, further comprising turning off the P-type metal-oxide-semiconductor transistor.

20. The method of claim 19, further comprising enabling the AND gate and passing the second differential output through the AND gate to control the N-type metal-oxide-semiconductor transistor.