×

Techniques for Enhancing Vertical Gate-All-Around FET Performance

  • US 20190172830A1
  • Filed: 12/06/2017
  • Published: 06/06/2019
  • Est. Priority Date: 12/06/2017
  • Status: Active Grant
First Claim
Patent Images

1. A method of forming a vertical field effect transistor (VFET) device, the method comprising the steps of:

  • patterning at least one fin in a substrate;

    forming bottom source and drains at a base of the at least one fin;

    forming bottom spacers on the bottom source and drains;

    forming a gate along sidewalls of the at least one fin;

    recessing the gate to expose a top portion of the at least one fin;

    forming an oxide layer along the sidewalls of the top portion of the at least one fin;

    depositing a charged layer over the at least one fin in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the at least one fin forming a dipole;

    forming top spacers above the gate; and

    forming top source and drains above the top spacers.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×