Techniques for Enhancing Vertical Gate-All-Around FET Performance
First Claim
1. A method of forming a vertical field effect transistor (VFET) device, the method comprising the steps of:
- patterning at least one fin in a substrate;
forming bottom source and drains at a base of the at least one fin;
forming bottom spacers on the bottom source and drains;
forming a gate along sidewalls of the at least one fin;
recessing the gate to expose a top portion of the at least one fin;
forming an oxide layer along the sidewalls of the top portion of the at least one fin;
depositing a charged layer over the at least one fin in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the at least one fin forming a dipole;
forming top spacers above the gate; and
forming top source and drains above the top spacers.
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Abstract
Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.
19 Citations
20 Claims
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1. A method of forming a vertical field effect transistor (VFET) device, the method comprising the steps of:
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patterning at least one fin in a substrate; forming bottom source and drains at a base of the at least one fin; forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the at least one fin; recessing the gate to expose a top portion of the at least one fin; forming an oxide layer along the sidewalls of the top portion of the at least one fin; depositing a charged layer over the at least one fin in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the at least one fin forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a VFET device, the method comprising the steps of:
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patterning at least one n-channel field-effect transistor (NFET) fin and at least one p-channel FET (PFET) fin in a substrate; forming NFET bottom source and drains at a base of the at least one NFET fin and PFET bottom source and drains at a base of the at least one PFET fins; forming bottom spacers on the NFET and PFET bottom source and drains; forming gates along sidewalls of the at least one NFET fin and along sidewalls of the at least one PFET fin; recessing the gates to expose top portions of the at least one NFET fin and the at least one PFET fin; forming an oxide layer along the sidewalls of the top portions of the at least one NFET fin and the at least one PFET fin; selectively forming a positively charged layer over the at least one NFET fin in contact with the oxide layer along the sidewalls of the top portions of the at least one NFET fin, wherein the positively charged layer induces a negative charge in the top portion of the at least one NFET fin forming a first dipole; selectively forming a negatively charged layer over the at least one PFET fin in contact with the oxide layer along the sidewalls of the top portions of the at least one PFET fin, wherein the negatively charged layer induces a positive charge in the top portion of the at least one PFET fin forming a second dipole; forming top spacers above the gate; and forming NFET and PFET top source and drains above the top spacers. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A VFET device, comprising:
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at least one fin patterned in a substrate; bottom source and drains at a base of the at least one fin; bottom spacers on the bottom source and drains; a gate along sidewalls of the at least one fin; an oxide layer formed along the sidewalls of a top portion of the at least one fin; a charged layer disposed over the at least one fin in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the at least one fin forming a dipole; top spacers above the gate; and top source and drains above the top spacers. - View Dependent Claims (18, 19, 20)
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Specification