NVM Architecture with OTA Support

• US 20190179629A1
• Filed: 12/12/2017
• Published: 06/13/2019
• Est. Priority Date: 12/12/2017
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Roy, Anirban, Jarrar, Anis M., Baker, JR., Frank K.
• Granted Patent: US 10,642,602 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
• CPC Class Codes: G06F 9/445 Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: H03M 7/30 Compression speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
• CPC Class Codes: H04L 67/12 specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
• CPC Class Codes: H04L 67/34 involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416
• CPC Class Codes: H04L 69/04 Protocols for data compression, e.g. ROHC

Abstract

A software update architecture, system, apparatus, and methodology are provided for performing block-based swapping of OTA software stored as a plurality of compressed blocks in a first, smaller NVM with the system software stored as a plurality of decompressed blocks in a second, larger NVM by using a first decompressor circuit and first scratch memory to sequentially decompress each compressed code block of OTA software for storage in decompressed form as updated system software in the second, larger NVM while using a first compressor circuit and second scratch memory to sequentially compress each decompressed code block of system software for storage in compressed form as backup system software in the first, smaller NVM.

Claims

1. A software update method comprising:

receiving over-the-air (OTA) software over a communications link at a device comprising;

a first nonvolatile memory operably disposed in the device for storing system software that is run on the device, the system software comprising a plurality of first code blocks that are not compressed, and

a second, smaller nonvolatile memory operably disposed in the device for storing the OTA software, the OTA software comprising a plurality of second code blocks that are compressed;

storing received OTA software in the second, smaller nonvolatile memory; and

performing block-based swapping of the OTA software in the second, smaller nonvolatile memory with the system software in the first nonvolatile memory using a first decompressor circuit to sequentially decompress each of the plurality of second code blocks of the OTA software for storage in decompressed form as updated system software in the first nonvolatile memory while, in a sequential fashion, a first compressor circuit sequentially compresses each of the plurality of first code blocks of the system software for storage in compressed form as backup system software in the second, smaller nonvolatile memory.

2. The software update method of claim 1, further comprising executing the updated system software stored in the first nonvolatile memory after performing block-based swapping of the OTA software with the system software.

3. The software update method of claim 1, further comprising reloading the system software into the first nonvolatile memory upon detecting an error in the updated system software by performing block-based swapping of the backup system software in the second, smaller nonvolatile memory with the updated system software in the first nonvolatile memory using the first decompressor circuit to sequentially decompress each block of backup system software stored in the second, smaller nonvolatile memory for storage in decompressed form in the first nonvolatile memory while, in a sequential fashion, the first compressor circuit sequentially compresses each block of updated system software stored in the first nonvolatile memory for storage in compressed form in the second, smaller nonvolatile memory.

4. The software update method of claim 1, where the second, smaller nonvolatile memory is half as large as the first nonvolatile memory.

5. The software update method of claim 1, where the first nonvolatile memory stores n m-byte blocks of decompressed code, where the second, smaller nonvolatile memory stores n p-byte blocks of compressed code, and where m>

p.

6. The software update method of claim 1, where performing block-based swapping comprises sequentially loading each of the plurality of second code blocks from the second, smaller nonvolatile memory into a first scratch memory and performing lossless decompression on each loaded second code block to generate a decompressed code block for storage in the first nonvolatile memory.

7. The software update method of claim 6, where performing block-based swapping comprises sequentially loading each of the plurality of first code blocks from the first nonvolatile memory into a second scratch memory and performing lossless compression on each loaded first code block to generate a compressed code block for storage in the second, smaller nonvolatile memory.

8. The software update method of claim 7, where the first scratch memory comprises a scratch nonvolatile memory, and where the second scratch memory comprises a scratch static random access memory (SRAM).

9. A device comprising:

a first nonvolatile memory storing system software as a first plurality of uncompressed code blocks that run on the device;

a second, smaller nonvolatile memory storing update software comprising a second plurality of compressed code blocks;

a first scratch memory for storing a compressed code block;

a second scratch memory for storing an uncompressed code block;

a decompressor circuit;

a compressor circuit; and

instruction memory for storing instructions which are executable and configured to perform block-based swapping of the update software in the second, smaller nonvolatile memory with the system software in the first nonvolatile memory by;

sequentially transferring each of the second plurality of compressed code blocks into the first scratch memory while sequentially transferring each of the first plurality of uncompressed code blocks into the second scratch memory, and

issuing commands to the decompressor circuit and compressor circuit to sequentially decompress each compressed code block in the first scratch memory for storage in uncompressed form as updated system software in the first nonvolatile memory while sequentially compressing a corresponding uncompressed code block in the second scratch memory for storage in compressed form as backup system software in the second, smaller nonvolatile memory.

10. The device of claim 9, where the first scratch memory comprises a scratch nonvolatile memory, and where the second scratch memory comprises a scratch static random access memory (SRAM).

11. The device of claim 9, where the second, smaller nonvolatile memory is half the size of the first nonvolatile memory.

12. The device of claim 9, where the first nonvolatile memory stores n m-byte uncompressed code blocks, where the second, smaller nonvolatile memory stores n p-byte compressed code blocks, and where m>

p.

13. The device of claim 9, where the decompressor circuit comprises a lossless decompressor circuit which sequentially loads each of the second plurality of compressed code blocks from the first scratch memory and performs lossless decompression on each compressed code block to generate an uncompressed code block for storage in the first nonvolatile memory.

14. The device of claim 9, where the compressor circuit comprises a lossless compressor circuit which sequentially loads each of the first plurality of uncompressed code blocks from the second scratch memory and performs lossless compression on each uncompressed code block to generate a compressed code block for storage in the second, smaller nonvolatile memory.

15. The device of claim 9, where issuing commands comprises issuing a first command to the compressor circuit to compress an uncompressed code block in the second scratch memory for storage in compressed form in the second, smaller nonvolatile memory, and then issuing a second command to the decompressor circuit to decompress a compressed code block in the first scratch memory for storage in uncompressed form in the first nonvolatile memory.

16. A nonvolatile memory architecture comprising:

a non-volatile memory (NVM) comprising a first NVM array which stores execution software as a first plurality of uncompressed code blocks and a second, smaller NVM array which stores compressed software as a second plurality of compressed code blocks;

a first scratch memory for storing a compressed code block;

a second scratch memory for storing an uncompressed code block;

a decompressor circuit; and

a compressor circuit;

where the decompressor circuit is connected to decompress each of the second plurality of compressed code blocks that is sequentially loaded from the first NVM array into the first scratch memory for storage in uncompressed form as updated execution software in the first NVM array in concert with the compressor circuit which is connected to compress each of the first plurality of uncompressed code blocks that is sequentially loaded into the second scratch memory for storage in compressed form as backup system software in the second, smaller NVM array, thereby performing block-based swapping of the compressed software in the second, smaller NVM array with the execution software in the first NVM array.

17. The nonvolatile memory architecture of claim 16, where the first scratch memory comprises a scratch nonvolatile memory, and where the second scratch memory comprises a scratch static random access memory (SRAM).

18. The nonvolatile memory architecture of claim 17, where the second, smaller NVM array is half the size of the first NVM array.

19. The nonvolatile memory architecture of claim 18, where the first NVM array stores n m-byte uncompressed code blocks, where the second, smaller NVM array stores n p-byte compressed code blocks, and where m>

p.

20. The nonvolatile memory architecture of claim 19, where the decompressor circuit comprises a lossless decompressor circuit which sequentially loads each of the second plurality of compressed code blocks from the first scratch memory and performs lossless decompression on each compressed code block to generate an uncompressed code block for storage in the first NVM array.

21. The nonvolatile memory architecture of claim 20, where the compressor circuit comprises a lossless compressor circuit which sequentially loads each of the first plurality of uncompressed code blocks from the second scratch memory and performs lossless compression on each uncompressed code block to generate a compressed code block for storage in the second, smaller NVM array.

22. The nonvolatile memory architecture of claim 16, where the first NVM array stores i m-byte uncompressed code blocks, where the second, smaller NVM array stores j p-byte compressed code blocks, where i≠

j, and where m>

p.