HIGH SPEED MEMORY INTERFACE

• US 20190179791A1
• Filed: 12/08/2017
• Published: 06/13/2019
• Est. Priority Date: 12/08/2017
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin, Holden, Brian, Stauffer, David
• Granted Patent: US 10,467,177 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: H04L 1/00 Arrangements for detecting or preventing errors in the information received correcting synchronisation H04L7/00

Abstract

Systems and methods for an Enhanced High Bandwidth Memory (EHBM) are described, utilizing fewer physical wires than a HBM interface with each wire operating at a much higher signaling rate. The same logical signals and commands of HBM are supported over this higher-speed transport, with the resulting lower wire count and reduced signal density allowing use of lower-cost interconnection such as an organic rather than a silicon interposer between GPU and DRAM stack.

Claims

1. A method comprising:

receiving a set of bits and an associated clock signal in parallel over a first multi-wire bus, the plurality of bits comprising data bits and control bits;

generating an augmented set of bits by augmenting the received set of bits with at least forward error correction (FEC) bits, the augmented set of bits comprising 5×

n×

m bits, wherein n and m are integers greater than or equal to 1;

generating a selector signal and at least one high-rate clock signal from the received associated clock signal, the selector signal and high-rate clock signal having a rate n times higher than the received clock signal;

generating n sets of m codewords, each set of m codewords generated in a respective transmission interval of n consecutive transmission intervals, wherein generating a given set of m codewords comprises;

selecting m sets of 5 bits from the augmented set of bits according to the selector signal; and

generating the given set of m codewords, each codeword generated based on a transformation of a respective set of 5 bits of the selected m sets of 5 bits with a non-simple orthogonal matrix; and

transmitting the n sets of m codewords according to the at least one high-rate clock signal over a second multi-wire bus, each of the sets of m codewords transmitted in a corresponding transmission interval, wherein the second multi-wire bus have a fewer number of wires than the first multi-wire bus.

2. The method of claim 1, wherein each codeword comprises 6 symbols.

3. The method of claim 2, wherein each symbol has a symbol value selected from a quaternary alphabet.

4. The method of claim 3, wherein the quaternary alphabet comprises symbol values selected from the set [±

1, ±

⅓

].

5. The method of claim 1, wherein n=8 sets of m=5 codewords are sent over n=8 transmission intervals.

6. The method of claim 1, wherein n=5 sets of m=8 codewords are sent over n=5 transmission intervals.

7. The method of claim 1, wherein the at least one high-rate clock signal comprises a single high-rate clock signal, and wherein each set of m codewords is transmitted according to the single high-rate clock signal.

8. The method of claim 1, wherein the at least one high-rate clock signal comprises m high-rate clock signals, and wherein each codeword of the given set of m codewords is transmitted according to a corresponding high-rate clock signal of the m high-rate clock signals.

9. The method of claim 1, wherein a subset of the n sets of m codewords are transmitted on unidirectional wires.

10. The method of claim 1, wherein a subset of the n sets of m codewords are transmitted on bidirectional wires.

11. An apparatus comprising:

a buffer configured to receive a set of bits in parallel over a first multi-wire bus, the plurality of bits comprising data bits and control bits;

a phase-locked loop configured to receive a clock signal associated with the received set of bits and to generate a selector signal and at least one high-rate clock signal from the received associated clock signal, the selector signal and high-rate clock signal having a rate nX higher than the received associated clock signal, wherein n is an integer greater than or equal to 1;

an augmentation circuit configured to receive the set of bits and to generate an augmented set of bits by augmenting the received set of bits with at least forward error correction (FEC) bits, the augmented set of bits comprising 5×

n×

m bits, wherein m is an integer greater than or equal to 1;

a selection circuit configured to receive the augmented set of bits, and to select m sets of 5 bits from the augmented set of bits according to the selector signal;

m encoders configured to generate n sets of m codewords, each set of m codewords generated in a respective transmission interval of n consecutive transmission intervals, wherein for a given set of m codewords, the encoder is configured to;

receive the selected m sets of 5 bits from the selection circuit; and

generate the given set of m codewords, each codeword generated based on a transformation of a respective set of 5 bits of the selected m sets of 5 bits with a non-simple orthogonal matrix; and

a plurality of drivers configured to transmit the n sets of m codewords according to the at least one high-rate clock signal over a second multi-wire bus, each of the sets of m codewords transmitted in a corresponding transmission interval, wherein the second multi-wire bus has a fewer number of wires than the first multi-wire bus.

12. The apparatus of claim 11, wherein each codeword comprises 6 symbols.

13. The apparatus of claim 12, wherein each symbol has a symbol value selected from a quaternary alphabet.

14. The apparatus of claim 13, wherein the quaternary alphabet comprises symbol values selected from the set [±

1, ±

⅓

].

15. The apparatus of claim 11, wherein n=8 sets of m=5 codewords are sent over n=8 transmission intervals.

16. The apparatus of claim 11, wherein n=5 sets of m=8 codewords are sent over n=5 transmission intervals.

17. The apparatus of claim 11, wherein the at least one high-rate clock signal comprises a single high-rate clock signal, and wherein the plurality of drivers is configured to transmit each set of m codewords according to the single high-rate clock signal.

18. The apparatus of claim 11, wherein the at least one high-rate clock signal comprises m high-rate clock signals, and wherein the plurality of drivers is configured to transmit each codeword of a given set of m codewords according to a corresponding high-rate clock signal of the m high-rate clock signals.

19. The apparatus of claim 11, wherein a subset of then sets of m codewords are received on unidirectional wires.

20. The apparatus of claim 11, wherein a subset of then sets of m codewords are received on bidirectional wires.