Three-dimensional Vertical NOR Flash Thin-Film Transistor Strings

• US 20190180821A1
• Filed: 02/20/2019
• Published: 06/13/2019
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: HARARI, ELI
• Granted Patent: US 10,395,737 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 : and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/16 : including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/40117 : the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 : Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6675 : Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/7926 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

Claims

1. A memory array formed above a substantially planar surface of a semiconductor substrate, the semiconductor substrate having circuitry formed therein, comprising a plurality of NOR-type memory strings, wherein each NOR-type memory string comprises a plurality of thin-film storage transistors sharing a common source region and a common drain region, the common source region and the common drain region each being a column of semiconductor material of a first conductivity type extending along a first direction that is substantially perpendicular to the planar surface, wherein (i) each thin-film storage transistor has a charge-trapping region, a channel region and a gate electrode that is isolated from the channel region by the charge-trapping region, and (ii) the gate electrodes of each thin-film storage transistors are each part of a corresponding one of a first set of conductors, each conductor extending along a second direction substantially parallel to the planar surface.

2. The memory array of claim 1, wherein the charge-trapping regions of the thin-film storage transistors are each a portion of a layer of charge-trapping material extending along the first direction.

3. The memory array of claim 2, wherein the channel regions of the thin-film storage transistors are each a portion of a layer of semiconductor material of a second conductivity type opposite the first conductivity type.

4. The memory array of claim 1, wherein the NOR-type memory strings are arrayed both along the second the direction and along a third direction also substantially parallel the planar surface and substantially orthogonal to the second direction.

5. The memory array of claim 1, wherein the common source region of each NOR-type memory string is electrically floating relative to the circuitry formed in the semiconductor substrate, except when one or more of the channel regions of the thin-film transistors of the NOR-type memory string is rendered conducting.

6. The memory array of claim 1, wherein each of the conductors is shared by gate electrodes of thin-film transistors in a plurality of the NOR-type memory strings of the memory array.

7. The memory circuit of claim 5, further comprising a second set of conductors extending along the third direction, wherein a first group of the second set of conductors each connect a portion of the circuitry in the semiconductor substrate to the common drain regions of selected one or more of the NOR-type memory strings in the memory array.

8. The memory array of claim 7, wherein the second set of conductors are formed between the memory array and the planar surface.

9. The memory array of claim 7, wherein the second set of conductors are formed above the memory array.

10. The memory array of claim 8, wherein the first group of the second set of conductors connect to the common drain regions of the selected memory arrays through select transistors.

11. The memory array of claim 8, wherein a second group of the second set of conductors connect corresponding ones of the first set of conductors through conductor-filled vias.

12. The memory array of claim 1, wherein each thin-film storage transistor has a data retention time shorter than a year and a program/erase cycle endurance greater than 10,000 program/erase cycles.

13. The memory array of claim 1, wherein each thin-film storage transistor has a native enhancement mode threshold voltage.

14. The memory array of claim 1, wherein the circuitry of the semiconductor substrate comprises voltage sources for providing predetermined voltages for memory operations.

15. The memory circuit of claim 14, wherein the predetermined voltages comprise voltages for program, program-inhibit, reading and erasing voltages.

16. The memory array of claim 1, wherein each thin-film storage transistor has a variable threshold voltage that is set using Fowler-Nordheim tunnelinRM-002-D4 g or direct tunneling.

17. The memory circuit of claim 16, wherein the variable threshold voltage is set to a level corresponding to one of two or more charge states.

18. The memory circuit of claim 1 wherein, in each NOR-type memory string, the common source region and the common drain region each include a dopant-blocking layer adjacent the channel region of each thin-film storage transistor.

19. The memory array of claim 18, wherein the dopant diffusion-blocking layer comprises a dielectric material that is less than three nanometers thick.

20. The memory array of claim 1, wherein the channel region of each thin-film storage transistor is electrically connected to the semiconductor substrate.

21. The memory circuit of claim 20, wherein the channel region of each thin-film storage transistor is connected to the semiconductor substrate by a pillar of semiconductor material of the first conductivity type.

22. The memory array of claim 20, wherein the semiconductor substrate provides the channel region of each thin-film storage transistor a predetermined back bias voltage that suppresses sub-threshold leakage during read operations.

23. The memory array of claim 1, wherein the channel region of each thin-film storage transistor has a length that is sufficiently short to effectuate erase through lateral hopping conduction and tunneling out of stored charge.

24. The memory array of claim 1, wherein the first set of conductors each comprise one of N⁺ doped polysilicon, P⁺ doped Polysilicon, a refractory metal of a high work function with respect to silicon dioxide, or silicides or polycides.

25. The memory array of claim 1, wherein the charge-trapping region comprises one or more layers of silicon nitride or a bandgap engineered oxide-nitride-oxide dielectric layer.

26. The memory array of claim 1, wherein each thin-film storage transistor of each NOR-type memory string is individually addressable for programming, programming-inhibiting, erasing or reading operations.

27. The memory array of claim 1, wherein the thin-film transistors are non-volatile or quasi-volatile.

28. The memory array of claim 1 wherein, during a read operation, an intrinsic capacitor of the common source region of each NOR-type memory string is charged to a virtual ground voltage and an intrinsic capacitor of the common drain region of the NOR-type memory string is charged to a read-sensing voltage,

29. The memory array of claim 28, wherein the gate electrode is raised to predetermined voltages to allow sensing of a threshold voltage of a selected thin-film storage transistor, while the gate electrodes of all other thin-film selected transistors of the NOR-type memory string are held at a non-conducting state.

30. The memory array of claim 28 wherein, during a programming operation, the intrinsic capacitors of the common source region and the common drain region are each momentarily pre-charged to a virtual ground voltage.

31. The memory array of claim 1, wherein one or more programming voltage pulses are applied selected one or more of the first set of conductors to initiate efficient Fowler-Nordheim tunneling or direct tunneling of charge from the channel region, the common source region and the common drain region to the charge-trapping region, while all other ones of the first set of conductors are held at a voltage that inhibits initiation of efficient Fowler-Nordheim tunneling or direct tunneling of charge from their channel regions, the common source, and the common drain region to the charge-trapping layer.

32. The memory array of claim 1, wherein the thin-film storage transistors of multiple NOR-type memory strings are erased in a single operation.

33. The memory array of claim 1, wherein one or more of the NOR-type memory strings serve as a reference memory string.

34. The memory array of claim 33, the circuitry in the semiconductor substrate comprise a differential sense amplifier which compares a signal received from a thin-film storage transistor in one of the NOR-type memory string and a signal received from a corresponding thin-film storage transistor of the reference NOR string.

35. The memory array of claim 33, wherein one or more thin-film storage transistors of the reference memory string are programmed to have set reference threshold voltages.

36. The memory array of claim 1, wherein one or more pf tje NOR-type memory strings are designated spare strings, each spare string being configurable to replace a NOR-type memory string in the memory array.

37. The memory string of claim 33, wherein threshold voltages programmed into thin-film storage transistors of the reference memory string correspond to programmed states under a multi-bit scheme.

38. The memory array of claim 1, wherein the channel region in each thin-film storage transistor is formed subsequent in time to forming the common drain region and the common source region.

39. The memory array of claim 38, wherein the channel region of each thin-film storage transistor has a length substantially determined by a thickness of a sacrificial layer removed.

40. The memory array of claim 1, wherein the circuitry in the semiconductor substrate comprise a data integrity circuit.

41. The memory array of claim 40, wherein the data integrity circuit comprises one or more of:

a data parity circuit and an error correcting circuit.