ACCIDENTAL FUSE PROGRAMMING PROTECTION CIRCUITS

• US 20190180833A1
• Filed: 02/20/2019
• Published: 06/13/2019
• Est. Priority Date: 11/02/2016
• Status: Abandoned Application

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Zhou, Bo, Blin, Guillaume Alexandre
• Application Number:
  US16/280,489
• Publication Number:
  US 20190180833A1
• Time in Patent Office: Days
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48229 the bond pad protruding from the surface of the item
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/1205 Capacitor
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1427 Voltage regulator [VR]
• CPC Class Codes: H01L 2924/1431 Logic devices
• CPC Class Codes: H01L 2924/145 Read-only memory [ROM]
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

Apparatus and methods for protection against inadvertent programming of fuse cells are provided herein. In certain configurations, a packaged radio frequency module includes a package substrate and a semiconductor die attached to the packaged substrate. The semiconductor die includes a power supply pad, a fuse, a fuse programming transistor having a source electrically connected to the power supply pad and a gate configured to receive a fuse programming signal, a cascode transistor electrically connected between a drain of the fuse programming transistor and the fuse, and a fuse protection capacitor electrically connected between the power supply pad and a gate of the cascode transistor and operable to inhibit unintended programming of the fuse.

Claims

1. A fuse system for a semiconductor die, the fuse system comprising:

a power supply pad configured to receive a power supply voltage;

a first fuse;

a first fuse programming transistor having a source electrically connected to the power supply pad and a gate configured to receive a fuse programming signal;

a first cascode transistor electrically connected between a drain of the first fuse programming transistor and the first fuse; and

a first fuse protection capacitor electrically connected between the power supply pad and a gate of the first cascode transistor, the first fuse protection capacitor operable to inhibit unintended programming of the first fuse.

2. The fuse system of claim 1 further comprising a voltage regulator configured to bias the gate of the first cascode transistor with a regulated voltage.

3. The fuse system of claim 2 wherein the voltage regulator generates the regulated voltage based on the power supply voltage, the first fuse protection capacitor operable to prevent accidental programming of the first fuse arising from a delay of the voltage regulator in providing voltage regulation.

4. The fuse system of claim 1 further comprising a programming logic circuit configured to generate the fuse programming signal based on a control signal.

5. The fuse system of claim 4 further comprising a serial interface configured to provide the control signal to the programming logic circuit to instruct programming of the first fuse.

6. The fuse system of claim 4 wherein the programming logic circuit includes a level shifter configured to control the fuse programming signal to a voltage level about equal to the power supply voltage in a first state of the control signal.

7. The fuse system of claim 1 further comprising a ground pad configured to receive a ground voltage, the first fuse electrically connected between a drain of the first cascode transistor and the ground pad.

8. The fuse system of claim 1 further comprising a plurality of core circuits powered by the power supply voltage from the power supply pad.

9. The fuse system of claim 1 further comprising a second fuse, a second fuse programming transistor having a source electrically connected to the power supply pad, and a second cascode transistor electrically connected between a drain of the second fuse programming transistor and the second fuse.

10. The fuse system of claim 9 wherein the first fuse programming capacitor is electrically connected between the power supply pad and a gate of the second cascode transistor and operable to inhibit unintended programming of the second fuse.

11. The fuse system of claim 9 further comprising a second fuse programming capacitor electrically connected between the power supply pad and a gate of the second cascode transistor and operable to inhibit unintended programming of the second fuse.

12. The fuse system of claim 9 further comprising a fuse sensing circuit having a first input electrically connected to the first fuse and a second input electrically connected to the second fuse.

13. A method of protecting against accidental fuse programming, the method comprising:

receiving a power supply voltage on a power supply pad of a semiconductor die;

biasing a gate of a fuse programming transistor using a fuse programming signal, the fuse programming transistor having a source electrically connected to the power supply voltage and a drain electrically connected to a fuse through a cascode transistor; and

inhibiting unintended programming of the fuse by adjusting a gate voltage of the cascode transistor using a fuse protection capacitor in response to a change in the power supply voltage, the fuse protection capacitor electrically connected between the power supply pad and a gate of the cascode transistor.

14. The method of claim 13 further comprising controlling the gate voltage of the cascode transistor using a regulated voltage from a voltage regulator, and using the fuse protection capacitor to prevent accidental programming of the fuse arising from a delay of the voltage regulator in providing voltage regulation.

15. The method of claim 13 further comprising generating the fuse programming signal based on a control signal using a programming logic circuit.

16. The method of claim 15 further comprising level shifting the control signal to generate the fuse programming signal, including controlling the fuse programming signal to a voltage level about equal to the power supply voltage in a first state of the control signal.

17. A packaged radio frequency module comprising:

a package substrate; and

a semiconductor die attached to the packaged substrate, the semiconductor die including a power supply pad, a fuse, a fuse programming transistor having a source electrically connected to the power supply pad and a gate configured to receive a fuse programming signal, a cascode transistor electrically connected between a drain of the fuse programming transistor and the fuse, and a fuse protection capacitor electrically connected between the power supply pad and a gate of the cascode transistor, the fuse protection capacitor operable to inhibit unintended programming of the fuse.

18. The packaged radio frequency module of claim 17 wherein the semiconductor die further includes a voltage regulator configured to bias the gate of the cascode transistor with a regulated voltage, the fuse protection capacitor operable to prevent accidental programming of the fuse arising from a delay of the voltage regulator in providing voltage regulation.

19. The packaged radio frequency module of claim 17 wherein the semiconductor die further includes a programming logic circuit configured to generate the fuse programming signal based on a control signal, and a serial interface configured to provide the control signal to the programming logic circuit to instruct programming of the fuse.

20. The packaged radio frequency module of claim 17 wherein the semiconductor die further includes a ground pad, the fuse electrically connected between a drain of the cascode transistor and the ground pad.