HIGH PERFORMANCE PLL BASED ON PVT INDEPENDENT STABLE OSCILLATOR

• US 20190181845A1
• Filed: 12/13/2017
• Published: 06/13/2019
• Est. Priority Date: 12/13/2017
• Status: Active Grant

• Current Assignee: Megachips Corporation
• Original Assignee: Megachips Corporation
• Inventors: Khare, Abhishek Kumar
• Granted Patent: US 10,447,253 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence

Abstract

A high performance phase-locked loop, the device includes a phase frequency detector, a charge pump, a loop filter, a first oscillator having inverters, configured to generate a first current, a second oscillator having a scaled version of the inverters of the first oscillator, a digital to analog converter, configured to generate a second current by multiplying the first current and a frequency code, a voltage to current converter, configured to generate a third current by converting voltage output of the loop filter to current, wherein input current to the second oscillator is sum of the second current and the third current.

Claims

1. A phase-locked loop comprising:

a phase frequency detector, a charge pump, a loop filter,

a first oscillator comprising inverters, configured to generate a first current,

a second oscillator comprising a scaled version of the inverters of the first oscillator,

a digital to analog converter, configured to generate a second current by multiplying the first current and a frequency code,

a voltage to current converter, configured to generate a third current by converting voltage output of the loop filter to current,

wherein input current to the second oscillator is sum of the second current and the third current.

2. The phase-locked loop of claim 1, wherein the frequency code is generated and stored during a training mode prior to the normal mode of the PLL, and wherein the voltage output of the loop filter is clamped during the training mode.

3. The phase-locked loop of claim 1, wherein the second oscillator is configured as a closed loop oscillator to generate the output frequency of the PLL.

4. The phase-locked loop of claim 1, wherein the frequency code is generated by comparing a reference clock frequency and a feedback clock frequency.

5. The phase-locked loop of claim 2, wherein the frequency code is generated by a frequency calibration block.

6. The phase-locked loop of claim 5, wherein the frequency calibration block is programmable to generate the frequency code corresponding to a factor of difference between the reference clock frequency and the feedback clock frequency.

7. The phase-locked loop of claim 5, wherein the frequency calibration block comprises a feedback divider code, a programmable divider, a free running counter, a code freeze register, a code comparator and a frequency code generator.

8. The phase-locked loop of claim 7, wherein the programmable divider generates a reset feedback pulse by dividing the reference clock frequency with feedback divider code, and

wherein the free running counter samples the feedback clock frequency based on the reset feedback and stores the generated code in the code freeze register.

9. The phase-locked loop of claim 8, wherein the code comparator generates a difference and a sign value based on comparison of the code in the code freeze register and the feedback divider code.

10. The phase-locked loop of claim 9, wherein the frequency code generator generates the frequency code based on the difference and the sign value generated by the code comparator.

11. The phase-locked loop of claim 10, wherein the training mode ends when the difference value becomes less than a specific value.

12. The phase-locked loop of claim 1, further comprising a level shifter connected to the output of the second oscillator.

13. The phase-locked loop of claim 2, wherein the training mode or the normal mode is selected based on a signal.

14. The phase-locked loop of claim 2, wherein the voltage output of the loop filter is clamped to a clamp voltage of a clamp voltage generator during the training mode.

15. The phase-locked loop of claim 2, wherein the phase frequency detector and the charge pump are tri-stated during the training mode.

16. A method of training a PLL for generating a frequency code comprising:

setting the frequency code to a default value;

asserting a clamp signal to tri-state a charge pump and a phase frequency detector of the PLL,

comparing a reference clock and a feedback clock using a frequency calibration block, wherein the frequency calibration block comprises a comparator and a frequency code generator,

updating the frequency code based on the comparison of the reference clock and the feedback clock, wherein the updation of the frequency code is performed till the difference between reference clock and the feedback clock is above a specified value,

locking and storing the frequency code once the difference between reference clock and the feedback clock is below the specified value, and

de-asserting the clamp signal to switch the charge pump and the phase frequency detector in a normal working mode.

17. The method of claim 16, wherein the comparator generates a difference and a sign value.

18. The method of claim 17, wherein the frequency code generator performs the updation on the basis of the difference and the sign value.

19. The method of claim 16, wherein the specified value is programmable.

20. A fast locking phase-locked loop producing low jitter comprising:

a phase frequency detector, a charge pump, a loop filter,

a first oscillator comprising odd number of inverters, configured as a low frequency open loop oscillator to generate the first current which is stable across process, voltage and temperature variation,

a second oscillator comprising a scaled version of the inverters of the first oscillator, configured as a closed loop current controlled high frequency oscillator to generate the output frequency of the PLL,

a frequency calibration block, configured to generate a frequency code by comparing a reference clock frequency and a feedback clock frequency,

a digital to analog converter, configured to generate a second current by multiplying the first current and the frequency code,

a voltage to current converter, configured to generate a third current by converting voltage output of the loop filter to current,

wherein input current to the second oscillator is sum of the second current and the third current, wherein the frequency code is generated and stored during a training mode prior to the normal mode of the PLL,

wherein the voltage output of the loop filter is clamped to a clamp voltage during the training mode.