LOW POWER LOGIC CIRCUITRY
First Claim
1. A combinational logic circuit within a programmable gate array, the combinational logic circuit comprising:
- first input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions, on a first node, between upper and lower voltages of a second voltage domain, the upper and lower voltages of the second voltage domain differing more than the upper and lower voltages of the first voltage domain; and
first output circuitry to generate, on a first output signal line, a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal on the first node,wherein the first input circuitry, the first node, and the first output circuitry are integrated within a first logic cell of the gate array and wherein the first node has a substantially lower capacitance than the first output signal line.
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Abstract
A combinational logic circuit includes input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions between upper and lower voltages of a second voltage domain. The combinational logic circuit additionally includes output circuitry to generate a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal.
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Citations
21 Claims
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1. A combinational logic circuit within a programmable gate array, the combinational logic circuit comprising:
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first input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions, on a first node, between upper and lower voltages of a second voltage domain, the upper and lower voltages of the second voltage domain differing more than the upper and lower voltages of the first voltage domain; and first output circuitry to generate, on a first output signal line, a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal on the first node, wherein the first input circuitry, the first node, and the first output circuitry are integrated within a first logic cell of the gate array and wherein the first node has a substantially lower capacitance than the first output signal line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of operation in a combinational logic circuit within a programmable gate array, the method comprising:
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receiving, via first input circuitry, a first input signal that transitions between upper and lower voltages of a first voltage domain generating, in response to the transitions of the first input signal, a first localized signal that transitions, on a first node, between upper and lower voltages of a second voltage domain, the upper and lower voltages of the second voltage domain differing more than the upper and lower voltages of the first voltage domain; and generating, within first output circuitry, a first output signal that transitions on a first output signal line between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal, wherein the first input circuitry, the first node, and the first output circuitry are integrated within a first logic cell of the programmable gate array and wherein the first node has a substantially lower capacitance than the first output signal line. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A combinational logic circuit within a programmable gate array, the combinational logic circuit comprising:
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means for receiving a first input signal that transitions between upper and lower voltages of a first voltage domain means for generating, in response to the transitions of the first input signal, a first localized signal that transitions, on a first node, between upper and lower voltages of a second voltage domain, the upper and lower voltages of the second voltage domain differing more than the upper and lower voltages of the first voltage domain; and means for generating, on a first output signal line, a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal; wherein the means for receiving the first input signal, the first node, and the means for generating the first output signal are integrated within a first logic cell of the programmable gate array and wherein the first node has a substantially lower capacitance than the first output signal line.
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Specification