Switchless Multi Input Stacked Transistor Amplifier Tree Structure

• US 20190190468A1
• Filed: 12/18/2017
• Published: 06/20/2019
• Est. Priority Date: 12/18/2017
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Shah, Khushali, Deng, Haopei
• Granted Patent: US 10,461,704 B2
• Time in Patent Office: Days
• CPC Class Codes: H01P 1/213 combining or separating two or more different frequencies H01P1/215 takes precedence
• CPC Class Codes: H01Q 23/00 Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H03F 1/22 by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/61 the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 3/16 with field-effect devices
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence

Abstract

Methods and devices for amplifying a plurality of input RF signals based on a multi-input cascode configuration is described. Transistors of stages of the multi-input cascode configuration are connected according to a tree, where there is at least one cascode transistor that is connected to at least two transistors of a stage below. In one case the stage below is an input stage, and in another case the stage below is a cascode stage. Activation and deactivation of transistors of the stages provide different conduction paths between the input stage and an output stage.

Claims

1. A multi-input cascode amplifier configuration comprising:

an input stage comprising a plurality of input transistors configured to receive a plurality of input RF signals; and

a plurality of cascode stages comprising an output stage,

wherein the input transistors of the input stage and cascode transistors of the plurality of cascode stages are connected according to a tree structure so that at least one cascode transistor of a first cascode stage of the plurality of cascode stages is coupled to at least two cascode transistors of a second cascode stage of the plurality of cascode stages.

2. The multi-input cascode configuration according to claim 1, wherein:

the input stage and the plurality of cascode stages are arranged in a sequence comprising the input stage as a bottom stage in the sequence, the output stage as a top stage in the sequence, and remaining stages of the plurality of cascode stages as one or more intermediate stages in the sequence, and

the first cascode stage is arranged above the second cascode stage in the sequence.

3. The multi-input cascode configuration according to claim 2, wherein the first cascode stage is the output stage.

4. The multi-input cascode configuration according to claim 3, wherein the second cascode stage is a stage that is coupled to the input stage.

5. The multi-input cascode configuration according to claim 2, wherein the first cascode stage is different from the output stage.

6. The multi-input cascode configuration according to claim 5, wherein the second cascode stage is a stage that is coupled to the input stage.

7. The multi-input cascode configuration according to claim 1, wherein the at least one cascode transistor of the first cascode stage is connected, via a source node of said transistor, to respective drain nodes of the at least two cascode transistors.

8. The multi-input cascode configuration according to claim 1, wherein the at least one cascode transistor of the first cascode stage comprises two transistors, each of the two transistors coupled to at least two respective transistors of the second cascode stage.

9. The multi-input cascode configuration according to claim 1, wherein:

at least one cascode transistor of the second cascode stage is connected to at least two transistors of a third stage comprising one of;

a) the plurality of cascode stages, and b) the input stage.

10. The multi-input cascode configuration according to claim 9, wherein the at least one cascode transistor of the second stage is one of the at least two transistors of the second cascode stage coupled to the at least one cascode transistor of the first cascode stage.

11. The multi-input cascode configuration according to claim 1, wherein:

during operation, the multi-input cascode configuration is configured to selectively provide, for each input transistor of the plurality of input transistors, a different conduction path between the each input transistor and a cascode transistor of the output stage according to a plurality of modes of operation comprising a first mode of operation and a second mode of operation,

during the first mode of operation, the different conduction path is a first conduction path that comprises one of the at least two transistors of the second cascode stage, and the at least one cascode transistor of the first cascode stage, and

during the second mode of operation, the different conduction path is a second conduction path that comprises the other of the at least two transistors of the second cascode stage, and the at least one cascode transistor of the first cascode stage.

12. The multi-input cascode configuration according to claim 11, wherein the different conduction path is selected based on:

activation of only one transistor of the plurality of transistors of the input stage,

activation of only one cascode transistor of each of the plurality of cascode stages, and

deactivation of remaining input transistors and remaining cascode transistors.

13. The multi-input cascode configuration according to claim 12, wherein the activation and deactivation is based on biasing voltages provided to gates of the input and cascode transistors.

14. The multi-input cascode configuration according to claim 11, wherein:

the plurality of modes of operation further comprises a third mode of operation that provides different conduction paths between two different input transistors of the plurality of input transistors of the input stage and one or more transistors of the output stage.

15. The multi-input cascode configuration according to claim 14, wherein the different conduction paths of the third mode of operation comprise the first conduction path and the second conduction path.

17. The multi-input cascode configuration according to claim 1, further comprising an inductor coupled at one end of the inductor, to at least two input transistors of the plurality of input transistors, and coupled at another end of the inductor, to a reference ground.

18. The multi-input cascode configuration according to claim 17, wherein the one end of the inductor is coupled to source nodes of the at least two input transistors.

19. A radio frequency (RF) circuital arrangement comprising a plurality of multi-input cascode configurations according to claim 1 arranged in parallel, comprising:

a common output node coupled to the output stage of each of the plurality of multi-input cascode configurations; and

a plurality of input nodes, each of the plurality of input nodes coupled to a respective input transistor of the plurality of input transistors of each of the plurality of multi-input cascode configurations,

wherein the plurality of input nodes are configured to receive the plurality of input RF signals, and

wherein the common output node is configured to provide an amplified version of an input RF signal of the plurality of input RF signals based on a selected mode of operation and a selected gain of the circuital arrangement.

20. The radio frequency (RF) circuital arrangement according to claim 19, wherein:

the selected gain is based on a number of multi-input cascode configurations of the plurality of multi-input cascode configurations that provide a current conduction path between the common output node and the amplified input RF, and

the selected mode is based on activated and deactivated transistors of the tree structure that provide the current conduction path, wherein a single transistor of each of the input stage and the one or more cascode stages of a respective multi-input cascode configuration is activated.

16. (canceled)

21. A method for amplifying a plurality of input RF signals according to at least two modes of operation, the method comprising:

providing an input stage comprising a plurality of input transistors configured to receive the plurality of input RF signals;

providing one or more cascode stages comprising an output stage;

connecting the input transistors of the input stage and cascode transistors of the one or more cascode stages;

based on the connecting, forming a tree structure so that at least one cascode transistor of a first cascode stage of the one or more cascode stages is coupled to at least two transistors of a second stage comprising one of;

a) the one or more cascode stages, and b) the input stage;

during a first mode of operation, providing a first conduction path between a first input RF signal of the plurality of input RF signals and the output stage, the first conduction path comprising the at least one cascode transistor of the first stage and one of the at least two transistors of the second stage, thereby amplifying the first input RF signal based on the first conduction path; and

during a second mode of operation, providing a second conduction path between a second input RF signal of the plurality of input RF signals and the output stage, the second conduction path comprising the at least one cascode transistor of the first stage and the other of the at least two transistors of the second stage, thereby amplifying the second input RF signal based on the second conduction path.

22. A multi-input cascode amplifier configuration comprising:

an input stage comprising a plurality of input transistors configured to receive a plurality of input RF signals; and

a plurality of cascode stages comprising an output stage,

wherein the input stage and the plurality of cascode stages are arranged in a sequence comprising the input stage as a bottom stage in the sequence and the output stage as the top stage in the sequence so to provide a tree structure having a plurality of different conduction paths from the input stage to the output stage,

wherein a number of cascode transistors of a first stage of the plurality of cascode stages is greater than a number of cascode transistors of a second stage of the plurality of cascode stages that is arranged immediately above the first stage.