LOAD REDUCED MEMORY MODULE
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Abstract
The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.
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Citations
21 Claims
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1. (canceled)
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2. A memory module comprising
a circuit board comprising a plurality of device sites, wherein each device site, of the plurality of device sites, is a location on the circuit board at which at least one respective memory device is disposed, wherein a first subset of the plurality of device sites is mapped to a first rank controlled by a first chip select (CS) signal and a second subset of the plurality of device sites is mapped to a second rank controlled by a second CS signal; -
a data buffer component disposed on the circuit board, the plurality of device sites being coupled to the data buffer component; and a command and address (CA) buffer component disposed on the circuit board, wherein the CA buffer component comprises; a first pin to receive the first CS signal from a memory controller component, the first CS signal to specify selection of at least one memory device disposed in the first subset of the plurality of device sites; and a second pin to receive the second CS signal from a second memory module via a private bus, the second CS signal to specify selection of at least one memory device disposed in the second subset of the plurality of device sites. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A memory system comprising:
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a memory controller component; a first memory module; a second memory module; a private bus coupled between the first memory module and the second memory module, wherein the first memory module comprises; a circuit board comprising a plurality of device sites, wherein each device site, of the plurality of device sites, is a location on the circuit board at which at least one respective memory device is disposed, wherein a first subset of the plurality of device sites is mapped to a first rank controlled by a first chip select (CS) signal and a second subset of the plurality of device sites is mapped to a second rank controlled by a second CS signal; a data buffer component disposed on the circuit board, the plurality of device sites being coupled to the data buffer component; and a command and address (CA) buffer component disposed on the circuit board, wherein the CA buffer component comprises; a first pin to receive the first CS signal from the memory controller component, the first CS signal to specify selection of at least one memory device disposed in the first subset of the plurality of device sites; and a second pin to receive the second CS signal from the second memory module via a private bus, the second CS signal to specify selection of at least one memory device disposed in the second subset of the plurality of device sites. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification