MICROELECTRONICS PACKAGE WITH AN INTEGRATED HEAT SPREADER

• US 20190198416A1
• Filed: 12/27/2017
• Published: 06/27/2019
• Est. Priority Date: 12/27/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Neal, Nicholas, Mendel, David W., Jha, Chandra M., Lofgreen, Kelly P.
• Granted Patent: US 10,461,011 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/3737 Organic materials with or without a thermoconductive filler
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a first die, a second die, and an integrated heat spreader. The integrated heat spreader may include a first surface. The first surface may define a first indentation located in between the first die and the second die.

Claims

1. A microelectronics package comprising:

a first die;

a second die;

a third die; and

an integrated heat spreader, the integrated heat spreader including a first surface, the first surface defining;

a first indentation located in between the first die and the second die, and

a second indentation located in between the third die and the first die and the second die.

2. The microelectronics package of claim 1, further comprising a filler located within the first indentation.

3. The microelectronics package of claim 2, wherein the filler has a thermal conductivity at least one order of magnitude less than a thermal conductivity of the integrated heat spreader.

4. The microelectronics package of claim 1, wherein the first indentation at least partially surrounds the first die or the second die.

5. The microelectronics package of claim 1, wherein the integrate heat spreader has a thickness and the first indentation has a depth of about 80% to about 95% of the thickness.

6. The microelectronics package of claim 1, wherein the first die has a first power density and the second die has a second power density, the first power density being at least one order of magnitude less than the second power density.

8. The microelectronics package of claim 1, wherein the first indentation and the second indentation each has a similar profile.

11. The microelectronics package of claim 1, further comprising a heat sink attached to a second surface of the integrated heat spreader.

12. The microelectronics package of claim 1, wherein the first indentation thermally isolates the first die from the second die.

26. The microelectronics package of claim 1, wherein the first indentation has a non-uniform profile.

27. The microelectronics package of claim 1, wherein the first die is a primary die and the second die is a high bandwidth memory die.

28. The microelectronics package of claim 1, wherein the first indentation and the second indentation each has a different profile.

7. (canceled)

9. (canceled)

10. (canceled)

13. A method of manufacturing a microelectronics package, the method comprising:

attaching a first die, a second die, and a third die to a substrate;

forming a first indentation in a first surface of an integrated heat spreader;

forming a second indentation in the integrated heat spreader; and

attaching the integrated heat spreader to the first die, the second die, and the third die such that;

the first indentation is located in between the first die and the second die, and

the second indentation is located in between the third die and the first die and the second die.

14. The method of claim 13, further comprising applying a filler within the first indentation.

15. The method of claim 13, wherein forming the first indentation includes forming the first indentation such that when the integrated heat spreader is attached to the first die and the second die, the first indentation at least partially surrounds the first die or the second die.

19. The method of claim 13, further comprising attaching a heat sink to a second surface of the integrated heat spreader.

16-18. -18. (canceled)

20-25. -25. (canceled)

30. A microelectronics package comprising:

a first die;

a second die;

a third die; and

an integrated heat spreader, the integrated heat spreader including a first surface, the first surface defining;

a first indentation located in between the first die and the second die,

a second indentation located in between the first die and the third die, and

a third indentation located in between the second die and the third die.

31. The microelectronics package of claim 30, wherein the first indentation and the second indentation each has a similar profile.

32. The microelectronics package of claim 30, wherein the first indentation at least partially surrounds the first die or the second die.

33. The microelectronics package of claim 30, wherein the first indentation has a non-uniform profile.

34. The microelectronics package of claim 30, wherein the first die is a primary die and the second die is a high bandwidth memory die.

35. The microelectronics package of claim 30, wherein the first indentation and the second indentation each has a different profile.

36. A method of manufacturing a microelectronics package, the method comprising:

attaching a first die, a second die, and a third die to a substrate;

forming a first indentation in a first surface of an integrated heat spreader;

forming a second indentation and a third indentation in the integrated heat spreader; and

attaching the integrated heat spreader to the first die, the second die, and the third die such that;

the first indentation is located in between the first die and the second die,

the second indentation is located in between the first die and the third die, and

the third indentation is located in between the second die and the third die

37. The method of claim 36, further comprising applying a filler within the first indentation.

38. The method of claim 36, wherein forming the first indentation includes forming the first indentation such that when the integrated heat spreader is attached to the first die and the second die, the first indentation at least partially surrounds the first die or the second die.